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AFE5805ZCFR Datasheet(PDF) 6 Page - Texas Instruments |
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AFE5805ZCFR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 52 page  AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com DIGITAL CHARACTERISTICS DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. At CLOAD = 5pF (1), I OUT = 3.5mA (2), R LOAD = 100Ω (2), and no internal termination, unless otherwise noted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 1.4 3.3 V Low-level input voltage 0 0.3 V High-level input current 10 mA Low-level input current(3) –10 mA Input capacitance 3 pF LVDS OUTPUTS High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 350 mV VOS output offset voltage (2) Common-mode voltage of OUTP and OUTM 1200 mV Output capacitance inside the device, Output capacitance 2 pF from either output to ground FCLKP and FCLKM 10 1x (clock rate) 50 MHz LCLKP and LCLKM 60 6x (clock rate) 300 MHz CLOCK Clock input rate 10 50 MSPS Clock duty cycle 50 % Clock input amplitude, differential Sine-wave, ac-coupled 3 VPP (VCLKP – VCLKM) LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Clock input amplitude, single-ended (VCLKP) High-level input voltage, VIH CMOS 2.2 V Low-level input voltage, VIL CMOS 0.6 V (1) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. (3) Except pin J3 (INT/EXT), which has an internal pull-up resistor (52k Ω) to 3.3V. 6 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): AFE5805 |
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