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DAC8718SRGZR Datasheet(PDF) 5 Page - Texas Instruments |
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DAC8718SRGZR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 60 page  DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSET DAC OUTPUT(15) (16) Voltage output VREF = +5V 0 5 V Full-scale error TA = +25°C ±4 LSB Zero-code error TA = +25°C ±2 LSB Linearity error ±6 LSB Differential linearity error ±1 LSB ANALOG MONITOR PIN (VMON) Output impedance(17) TA = +25°C 2 k Ω Three-state leakage current 100 nA AUXILIARY ANALOG INPUT Input range AVSS AVDD V Input impedance TA = +25°C 2 k Ω (AIN-x to VMON) Input capacitance(15) 4 pF Input leakage current 30 nA REFERENCE INPUT Reference input voltage range(18) 1.0 5.5 V Reference input dc impedance 10 M Ω Reference input capacitance(15) 10 pF DIGITAL INPUT(15) IOVDD = +4.5V to +5.5V 3.8 0.3 + IOVDD V High-level input voltage, VIH IOVDD = +2.7V to +3.3V 2.3 0.3 + IOVDD V IOVDD = +1.7V to 2.0V 1.5 0.3 + IOVDD V IOVDD = +4.5V to +5.5V –0.3 0.8 V Low-level input voltage, VIL IOVDD = +2.7V to +3.3V –0.3 0.6 V IOVDD = +1.7V to 2.0V –0.3 0.3 V CLR, LDAC, RST, CS, and SDI ±1 μA Input current USB/BTC, RSTSEL, and GPIO-n ±5 μA CLR, LDAC, RST, CS, and SDI 5 pF Input capacitance USB/BTC and RSTSEL 12 pF GPIO-n 14 pF DIGITAL OUTPUT(15) IOVDD = +2.7V to +5.5V, sourcing 1mA IOVDD – 0.4 IOVDD V High-level output voltage, VOH (SDO) IOVDD = +1.8V, sourcing 200μA 1.6 IOVDD V IOVDD = +2.7V to +5.5V, sinking 1mA 0 0.4 V Low-level output voltage, VOL (SDO) IOVDD = +1.8V, sinking 200μA 0 0.2 V GPIO-n output voltage low, VOL 1mA sink from IOVDD 0.15 V GPIO-n output voltage high, VOH 10k Ω pull-up resistor to IOVDD 0.99 × IOVDD V High-impedance leakage current SDO and GPIO-n ±5 μA SDO 5 pF High-impedance output capacitance GPIO-n 14 pF (15) Specified by design. (16) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary no more than ±10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and must not be connected during dual-supply operation. (17) 8k Ω when VMON is connected to Reference Buffer A or B, and 4kΩ when VMON is connected to Offset DAC-A or -B. (18) Reference input voltage ≤ DVDD. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): DAC8718 |
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