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DAC8718SPAG Datasheet(PDF) 3 Page - Texas Instruments |
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DAC8718SPAG Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 60 page  DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(2) Resolution 16 Bits Linearity error Measured by line passing through codes 0000h and FFFFh ±4 LSB Differential linearity error Measured by line passing through codes 0000h and FFFFh ±1 LSB TA = +25°C, before user calibration, gain = 6, code = 8000h ±10 LSB Bipolar zero error TA = +25°C, before user calibration, gain = 4, code = 8000h ±15 LSB TA = +25°C, after user calib., gain = 4 or 6, code = 8000h ±1 LSB Bipolar zero error TC Gain = 4 or 6, code = 8000h ±0.5 ±2 ppm FSR/°C TA = +25°C, gain = 6, code = 0000h ±10 LSB Zero-code error TA = +25°C, gain = 4, code = 0000h ±15 LSB Zero-code error TC Gain = 4 or 6, code = 0000h ±0.5 ±3 ppm FSR/°C TA = +25°C, gain = 6 ±10 LSB Gain error TA = +25°C, gain = 4 ±15 LSB Gain error TC Gain = 4 or 6 ±1 ±3 ppm FSR/°C TA = +25°C, before user calibration, gain = 6, code = FFFFh ±10 LSB Full-scale error TA = +25°C, before user calibration, gain = 4, code = FFFFh ±15 LSB TA = +25°C, after user calib., gain = 4 or 6, code = FFFFh ±1 LSB Full-scale error TC Gain = 4 or 6, code = FFFFh ±0.5 ±3 ppm FSR/°C Measured channel at code = 8000h, full-scale change on any DC crosstalk(3) 0.2 LSB other channel (1) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary no more than ±10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and must not be connected during dual-supply operation. (2) Gain = 4 and TC specified by design and characterization. (3) The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): DAC8718 |
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