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LTC4280IUFD-TRPBF Datasheet(PDF) 8 Page - Linear Technology |
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LTC4280IUFD-TRPBF Datasheet(HTML) 8 Page - Linear Technology |
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8 / 28 page  LTC4280 8 4280f PIN FUNCTIONS ADIN: ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to ground if unused. ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying these pins to ground, to the INTVCC pin or open configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register. See Applications Information. Tie to ground if unused. EN: Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10μA current source pulls up this pin. Transitions on this pin are recorded in the Fault register. A high-to-low transition activates the logic to read the state of the ON pin and clear Faults. See Applications Information. EXPOSED PAD (Pin 25): Exposed pad may be left open or connected to device ground. FB: Foldback Current Limit and Power Good Input. A resistive divider from the output is tied to this pin. When the voltage at this pin drops below 1.235V, power is not considered good. The power bad condition may result in the GPIO pin pulling low or going high impedance depending on the configuration of control register bits A6 and A7. Also a power bad fault is logged in this condition if the LTC4280 has finished the start-up cycle and the GATE pin is high. See Applications Information. The current limit folds back from a 26mV sense voltage to 10mV as the FB pin voltage falls from 0.6V to 0V. FILTER: Fault Filter Input. Connect a capacitor between this pin and ground to set a 123ms/μF delay for overcurrent fault filtering after startup. GATE: Gate Drive for External N-Channel MOSFET. An internal 20μA current source charges the gate of the MOSFET. Often no compensation capacitor is required on the GATE pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. See Applications Information. During turn-off there is a 1mA pulldown current. During a short-circuit or undervoltage lockout (VDD or INTVCC), a 450mA pulldown current source between GATE and SOURCE is activated. GND: Device Ground. GPIO: General Purpose Input/Output. Open-drain logic output or logic input. Defaults to an output set to pull low to indicate power is not good. Configure according to Table 2 and 3. INTVCC: Low Voltage Supply Decoupling Output. Connect a 0.1μF capacitor from this pin to ground. ON: On Control Input. A rising edge turns on the external N-channel MOSFET and a falling edge turns it off. This pin also configures the state of the FET On bit in the control register (and hence the external MOSFET) at power up. For example, if the ON pin is tied high, then the FET On bit (A3 in Table 2) goes high 100ms after power-up. Likewise if the ON pin is tied low then the part remains off after power-up until the FET On bit is set high using the I2C bus. A high-to-low transition on this pin clears the fault register. OV: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage fault is detected and the GATE turns off. Tie to GND if unused. |
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