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LT3579IFE-TRPBF Datasheet(PDF) 11 Page - Linear Technology |
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LT3579IFE-TRPBF Datasheet(HTML) 11 Page - Linear Technology |
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11 / 40 page  LT3579/LT3579-1 11 35791f Sample Mode Sample Mode is the mechanism used by the LT3579 to aid in the detection of output shorts. It refers to a state of the LT3579 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch current limit of 3.4A (minimum), the LT3579 triggers an overcurrent fault internally (see Operation-Fault section for details). Sample Mode exists when FB is out of regulation by more than 3.7% or 45mV < FB < 1.17V (typical). The LT3579’s power switches are designed to handle a total peak current of 6A (minimum). Frequency Foldback The frequency foldback circuit reduces the switching frequency when 350mV < FB < 900mV (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current during start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal. Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target VOUT,VIN,switchingfrequency,etc.Test the application’s performance at start-up to ensure that the peak inductor current does not exceed the minimum current limit. OPERATION – REGULATION The following description of the LT3579’s operation assumes the FB voltage is close enough to its regulation target so that the part is not in Sample Mode. Use the Block Diagram as a reference when stepping through the following description of the LT3579 operating in regulation. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switches Q1 and Q2. The collector current through the master switch, Q1, is ~1.3 times the collector current through the slave switch, Q2, when the collectors of the two switches are tied together. Q1’s emitter current flows through a current OPERATION sense resistor (RS) generating a voltage proportional to the total switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When the voltage on the positive input of A3 exceeds the voltage on the negative input, the SR latch is reset, turning off the master and slave power switches. The voltage on the negative input of A3 (VC pin) is set by A1 (or A2), which is simply an amplified difference between the FB pin voltage and the reference voltage (1.215V if the LT3579 is configured as a boost converter, or 9mV if configured as an inverting converter). In this manner, the error amplifer sets the correct peak current level to maintain output regulation. As long as the part is not in fault (see Operation – FAULT section) and the SS pin exceeds 1.8V, the LT3579 drives its CLKOUT pin at the frequency set by the RT pin or the SYNC pin. The CLKOUT pin can synchronize other compatible switching regulator ICs (including additional LT3579s) with the LT3579. Additionally, the duty cycle of CLKOUT varies linearly with the part’s junction temperature and may be used as a temperature monitor. The CLKOUT signal on the LT3579-1 is ~180° out of phase with the internal oscillator and has a fixed duty cycle of ~50%. OPERATION – FAULT The LT3579’s FAULT pin is an active low, bidirectional pin (refer to Block Diagram) that pulls low to indicate a fault. Each of the following events can trigger a fault in the LT3579: A. FAULT1 Events: 1. SW Overcurrent a. ISW1 > 3.4A (minimum) b. (ISW1 + ISW2) > 6A (minimum) 2. VIN Voltage > 16.2V (minimum) 3. SW1 Voltage and/or SW2 Voltage > 42V (minimum) 4. Die Temperature > 165°C B. FAULT2 Events: 1. Pulling the FAULT pin low externally |
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