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DFC15U48S15 Datasheet(PDF) 2 Page - Power-One |
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2 / 3 page 2 s r e t e m a r a P t u p n I ) 1 ( l e d o M 5 S 8 4 U 5 1 C F D 2 1 S 8 4 U 5 1 C F D 5 1 S 8 4 U 5 1 C F D s t i n U e g n a R e g a t l o V N I M P Y T X A M 0 . 0 2 0 . 8 4 0 . 0 6 C D V d a o L ll u F t n e r r u C t u p n I d a o L o N P Y T P Y T 0 5 9 2 5 1 9 4 5 0 9 4 A m y c n e i c i f f EP Y T9 72 83 8% y c n e u q e r F g n i h c t i w SP Y T0 2 1z H k s m 0 0 1 , e g a t l o v r e v O t u p n I m u m i x a M e g a m a D o N X A M5 7C D V r o r r E t u p t u O % 1 , e m i T n o - n r u TP Y T5 0 1s m s r e t e m a r a P t u p t u O ) 1 ( l e d o M 5 S 8 4 U 5 1 C F D 2 1 S 8 4 U 5 1 C F D 5 1 S 8 4 U 5 1 C F D s t i n U e g a t l o V t u p t u O5 2 15 1C D V ) 3 ( d a o L d e t a R N I M X A M 0 0 0 0 3 0 0 5 2 1 0 0 0 0 1 A m e g n a R e g a t l o V d a o L % 0 0 1 N I M P Y T X A M 5 9 . 4 0 0 . 5 5 0 . 5 0 9 . 1 1 0 0 . 2 1 0 1 . 2 1 0 9 . 4 1 0 0 . 5 1 0 1 . 5 1 C D V n o i t a l u g e R d a o L d a o L ll u F % 0 0 1 - 5 2 P Y T X A M 5 . 0 5 7 . 0 1 . 0 2 . 0 1 . 0 2 . 0 % n o i t a l u g e R e n i L C D V x a M - n i M = n i V P Y T X A M 1 . 0 5 1 . 0 1 0 . 0 1 . 0 1 0 . 0 1 . 0 % ) 4 ( y t il i b a t S m r e T t r o h SP Y T2 0 . 0 <s r H 4 2 / % y t il i b a t S m r e T g n o LP Y T5 0 . 0 <s r H k / % ) 5 ( n o i t c e j e R e l p p i R t u p n IP Y T0 6 >B d ) 2 ( w b z H M 0 2 - 0 , e s i o NP Y T5 70 60 6V m P P e s i o N S M RP Y T3 2 2 V m s m r t n e i c i f f e o C e r u t a r e p m e T P Y T X A M 0 5 0 5 1 / m p p °C n o i t c e t o r P t i u c r i C t r o h S T U O - o t T U O + t i m i L t n e r r u C s u o u n i t n o C NOTES (1) All Parameters measured at Tc=25°C, nominal input voltage and full rated load unless otherwise noted. Refer to the Technical Reference Section for the definition of terms, measurement circuits and other information. (2) Noise is measured per Technical Reference Section. Measurement bandwidth is 0-20 MHz. RMS noise is measured over a 0.01-1 MHz bandwidth. To simulate standard PCB decoupling practices, output noise is measured with a 1µF/35V tantalum capacitor located 1 inch away from the converter. (3) Minimum load required for rated regulation only. Dynamic response may degrade if run at less than 25% full load. (4) Short term stability is specified after a 30 minute warm-up at full load, and with constant line, load and ambient conditions. (5) The input ripple rejection is specified for DC to 120Hz ripple with a modulation amplitude of 1% Vin. DFC15 SERIES APPLICATION NOTES: External Capacitance Requirements No external capacitance is required for operation of the DFC15 Series. However, for maximum performance, it is recommended that the DFC15 Series use a capacitor of sufficient ripple current capacity connected across the input pins if a capacitive input source is farther than 1” from the converter. To meet the reflected ripple requirements of the converter, an input impedance of less than 0.05 Ohms from DC to 200KHz is required. External output capacitance is not required for operation, however it is recommended that 1 F to 10 F of tantalum and 0.001 to 0.1 F ceramic capacitance be selected for reduced system noise. Additional output capacitance may be added for increased filtering, but should not exceed 400 F. Negative Outputs A negative output voltage may be obtained by connecting the +OUT to circuit ground and connecting -OUT as the negative output. (continued) DFC15 SERIES – SINGLE OUTPUT |
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