Pin Name

Pin #

I/O, Type

Description

VODSEL

20

I, LVCMOS

w/ pull-down

Differential Driver Output Voltage Select — Pin or Register Control

VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications

VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)

De-Emph

19

I, Analog

w/ pull-up

De-Emphasis Control — Pin or Register Control

De-Emph = open (float) - disabled

To enable De-emphasis, tie a resistor from this pin to GND or control via register.

See Table 4

MAPSEL

26

I, LVCMOS

w/ pull-down

Channel Link Map Select — Pin or Register Control

MAPSEL = 1, MSB on RxIN3+/-. Figure 22

MAPSEL = 0, LSB on RxIN3+/-. Figure 21

CONFIG

[1:0]

10, 9

I, LVCMOS

w/ pull-down

Operating Modes — Pin or Limited Register Control

Determines the device operating mode and interfacing device. Table 1

CONFIG[1:0] = 00: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter

DISABLED

CONFIG[1:0] = 01: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter

ENABLED

CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124

CONFIG [1:0] = 11: Interfacing to DS90C124

ID[x]

4

I, Analog

Serial Control Bus Device ID Address Select — Optional

Resistor to Ground and 10 k

Ω pull-up to 1.8V rail. See Table 10.

SCL

6

I, LVCMOS

Serial Control Bus Clock Input - Optional

SCL requires an external pull-up resistor to V

SDA

7

I/O, LVCMOS

Open Drain

Serial Control Bus Data Input / Output - Optional

SDA requires an external pull-up resistor V

BISTEN

21

I, LVCMOS

w/ pull-down

BIST Mode — Optional

BISTEN = 1, BIST is enabled

BISTEN = 0, BIST is disabled

RES[7:0]

25, 3, 36, 27,

18, 13, 12, 8

I, LVCMOS

w/ pull-down

Reserved - tie LOW

Channel Link II Serial Interface

DOUT+

16

O, CML

True Output.

The output must be AC Coupled with a 0.1

μF capacitor.

DOUT-

15

O, CML

Inverting Output.

The output must be AC Coupled with a 0.1

μF capacitor.

Power and Ground

VDDL

5

Power

Logic Power, 1.8 V ±5%

VDDP

11

Power

PLL Power, 1.8 V ±5%

VDDHS

14

Power

TX High Speed Logic Power, 1.8 V ±5%

VDDTX

17

Power

Output Driver Power, 1.8 V ±5%

VDDRX

24

Power

RX Power, 1.8 V ±5%

VDDIO

22

Power

LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%

GND

DAP

Ground

DAP is the large metal contact at the bottom side, located at the center of the LLP

package. Connect to the ground plane (GND) with at least 9 vias.

NOTE: 1= HIGH, 0 L= LOW

The VDD (V

on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.

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