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PIC16F785 Datasheet(PDF) 11 Page - Microchip Technology |
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PIC16F785 Datasheet(HTML) 11 Page - Microchip Technology |
11 / 206 page © 2008 Microchip Technology Inc. DS41249E-page 9 PIC16F785/HV785 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F785/HV785 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC16F785/HV785 is physically implemented. Access- ing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F785/HV785 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static RAM. The last sixteen register locations in Bank 1 (F0h-FFh), Bank 2 (170h-17Fh), and Bank 3 (1F0h-1FFh) point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. Seven address bits are required to access any location in a data memory bank. Two additional bits are required to access the four banks. When data memory is accessed directly, the seven Least Significant address bits are contained within the opcode and the two Most Significant bits are contained in the STATUS register. RP0 and RP1 bits of the STATUS register are the two Most Significant data memory address bits and are also known as the bank select bits. Table 2-1 lists how to access the four banks of registers. TABLE 2-1: BANK SELECTION 2.2.1 GENERAL PURPOSE REGISTER FILE The register file banks are organized as 128 x 8 in the PIC16F785/HV785. Each register is accessed, either directly, by seven address bits within the opcode, or indirectly, through the File Select Register (FSR). When the FSR is used to access data memory, the eight Least Significant data memory address bits are contained in the FSR and the ninth Most Significant address bit is contained in the IRP bit in the STATUS Register. (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-2). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. PC<12:0> 13 0000h 0004 0005 07FFh 0800h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory CALL, RETURN RETFIE, RETLW Stack Level 2 RP1 RP0 Bank 0 00 Bank 1 01 Bank 2 10 Bank 3 11 |
Similar Part No. - PIC16F785_08 |
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Similar Description - PIC16F785_08 |
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