Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

11LC161-ISN Datasheet(PDF) 9 Page - Microchip Technology

Part # 11LC161-ISN
Description  1K-16K UNI/O짰 Serial EEPROM Family Data Sheet
Download  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

11LC161-ISN Datasheet(HTML) 9 Page - Microchip Technology

Back Button 11LC161-ISN Datasheet HTML 5Page - Microchip Technology 11LC161-ISN Datasheet HTML 6Page - Microchip Technology 11LC161-ISN Datasheet HTML 7Page - Microchip Technology 11LC161-ISN Datasheet HTML 8Page - Microchip Technology 11LC161-ISN Datasheet HTML 9Page - Microchip Technology 11LC161-ISN Datasheet HTML 10Page - Microchip Technology 11LC161-ISN Datasheet HTML 11Page - Microchip Technology 11LC161-ISN Datasheet HTML 12Page - Microchip Technology 11LC161-ISN Datasheet HTML 13Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 44 page
background image
 2010 Microchip Technology Inc.
Preliminary
DS22067H-page 9
11AAXXX/11LCXXX
3.6
Device Standby
The 11XX features a low-power Standby mode during
which the device is waiting to begin a new command.
A high-to-low transition on SCIO will exit low-power
mode and prepare the device for receiving the start
header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid termina-
tion of a command)
• Reception of a standby pulse
3.7
Device Idle
The 11XX features an Idle mode during which all serial
data is ignored until a standby pulse occurs. Idle mode
will be entered upon the following conditions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle.
• Missed edge transition
• Reception of a MAK following a
WREN, WRDI,
SETAL, or ERAL command byte
• Reception of a MAK following the data byte of a
WRSR command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
3.8
Synchronization
At the beginning of every command, the 11XX utilizes
the start header to determine the master’s bus clock
period. This period is then used as a reference for all
subsequent communication within that command.
The 11XX features re-synchronization circuitry which
will monitor the position of the middle data edge during
each MAK bit and subsequently adjust the internal time
reference in order to remain synchronized with the
master.
There are two variables which can cause the 11XX to
lose synchronization. The first is frequency drift,
defined as a change in the bit period, TE. The second is
edge jitter, which is a single occurrence change in the
position of an edge within a bit period, while the bit
period itself remains constant.
3.8.1
FREQUENCY DRIFT
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some toler-
ance for such frequency drift. The tolerance range is
specified by two parameters, FDRIFT and FDEV. FDRIFT
specifies the maximum tolerable change in bus fre-
quency per byte. FDEV specifies the overall limit in fre-
quency deviation within an operation (i.e., from the end
of the start header until communication is terminated
for that operation). The start header at the beginning of
the next operation will reset the re-synchronization cir-
cuitry and allow for another FDEV amount of frequency
drift.
3.8.2
EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization cir-
cuitry is designed to provide some tolerance for edge
jitter.
The 11XX adjusts its phase every MAK bit, so TIJIT
specifies the maximum allowable peak-to-peak jitter
relative to the previous MAK bit. Since the position of
the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be cal-
culated and then compared against TIJIT to determine
jitter compliance.
Note: In the case of the
WRITE, WRSR, SETAL, or
ERAL commands, the write cycle is initiated
upon receipt of the NoMAK, assuming all
other write requirements have been met.
Note: Because the 11XX only re-synchronizes
during the MAK bit, the overall ability to
remain synchronized depends on a combi-
nation of frequency drift and edge jitter (i.e.,
if the MAK bit edge is experiencing the max-
imum allowable edge jitter, then there is no
room for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no edge
jitter can be present.


Similar Part No. - 11LC161-ISN

ManufacturerPart #DatasheetDescription
logo
Microchip Technology
11LC161-I/SN MICROCHIP-11LC161-I/SN Datasheet
830Kb / 44P
   1K-16K UNI/O Serial EEPROM Family Data Sheet
01/05/10
More results

Similar Description - 11LC161-ISN

ManufacturerPart #DatasheetDescription
logo
Microchip Technology
11AA010 MICROCHIP-11AA010 Datasheet
597Kb / 38P
   1K-16K UNI/O짰 Serial EEPROM Family Data Sheet
2008
11AA010 MICROCHIP-11AA010_11 Datasheet
757Kb / 48P
   1K-16K UNI/O짰 Serial EEPROM Family Data Sheet
2011
11AA020T-I MICROCHIP-11AA020T-I Datasheet
830Kb / 44P
   1K-16K UNI/O Serial EEPROM Family Data Sheet
01/05/10
25LC010A MICROCHIP-25LC010A_09 Datasheet
348Kb / 24P
   1K-4K SPI Serial EEPROM High Temp Family Data Sheet
2009
24LC02BT-ISNG MICROCHIP-24LC02BT-ISNG Datasheet
834Kb / 42P
   I2C??Serial EEPROM Family Data Sheet
06/25/07
24AA025 MICROCHIP-24AA025 Datasheet
814Kb / 42P
   I2C??Serial EEPROM Family Data Sheet
2007
11AA02UID MICROCHIP-11AA02UID Datasheet
666Kb / 32P
   2K UNI/O짰 Serial EEPROM with Unique 32-Bit Serial Number
11/29/12
11AA02E48 MICROCHIP-11AA02E48 Datasheet
277Kb / 18P
   2K UNI/O짰 Serial EEPROM with EUI-48??Node Identity
2008
logo
Catalyst Semiconductor
CAT24WC01 CATALYST-CAT24WC01_05 Datasheet
505Kb / 14P
   1K/2K/4K/8K/16K-Bit Serial EEPROM
logo
List of Unclassifed Man...
TMC93LC46 ETC-TMC93LC46 Datasheet
1Mb / 15P
   1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com