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LPC1754FBD80 Datasheet(PDF) 9 Page - NXP Semiconductors |
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LPC1754FBD80 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 835 page  UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 9 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 6. Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. Details of the multilayer matrix connections are shown in Figure 1–2. APB peripherals are connected to the CPU via two APB busses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller. The APB bus bridges are configured to buffer writes so that the CPU or DMA controller can write to APB devices without always waiting for APB write completion. 7. ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with Wakeup Interrupt Controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is appended to this manual. 7.1 Cortex-M3 Configuration Options The LPC17xx uses the r2p0 version of the Cortex-M3 CPU, which includes a number of configurable options, as noted below. System options: • The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the SYSTICK timer. • The Wakeup Interrupt Controller (WIC) is included. The WIC allows more powerful options for waking up the CPU from reduced power modes. • A Memory Protection Unit (MPU) is included. • A ROM Table in included. The ROM Table provides addresses of debug components to external debug systems. Debug related options: |
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