Internal-Switch Boost Regulator with Integrated

7-Channel Scan Driver, Op Amp, and LDO

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Pin Configuration

Pin Description

MAX17117

THIN QFN

TOP VIEW

29

30

28

27

12

11

13

14

1

+

2

IN

4

5

6

7

23

24

22

20

19 18

LDOO

LDOADJ

CKH2

CKH3

CKH4

CKH5

3

21

31

10

DTS

CKH6

32

9

SS

EP

VGLC

ENA

26

15 CKH1

LX

25

16 STH

8

17

PGND

PIN

NAME

FUNCTION

1–5, 7

CK5–CK1,

CK6

Level-Shifter Logic-Level Inputs

6

ST

Start-Pulse, Level-Shifter Logic-Level Input

8

RE

Gate-Shading Discharge for CKH2, CKH4, and CKH6

9

VGLC

VGL Voltage Output

10–15

CKH6–CKH1

Level-Shifter Outputs

16

STH

Start-Pulse Level-Shifter Output

17

VGL

Gate-Off Supply. VGL is the negative supply voltage for the STH, CKH1–CKH6, and VGLC high-volt-

age driver outputs. Bypass to PGND with a minimum of 0.1FF ceramic capacitor.

18

GHON

Gate-On Supply. GHON is the positive supply voltage for the STH, CKH1–CKH6, and VGLC high-

voltage scan-driver outputs. Bypass to PGND with a minimum of 0.1FF ceramic capacitor.

19

RO

Gate-Shading Discharge for CKH1, CKH3, and CKH5

20

OUT

Operational Amplifier Output

21

POS

Operational Amplifier Noninverting Input

22

OPAS

greater ceramic capacitor.

23

COMP

Compensation for Error Amplifier. Connect a series RC from this pin to AGND. Typical values are

56kI and 1000pF.

24

FB

Step-Up Regulator Feedback. Reference voltage is 1.24V nominal. Connect the midpoint of an exter-