Compact, Low-Cost 1S/2S Fuel Gauges

with Low-Battery Alert

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11

2-Wire Bus System

The 2-wire bus system supports operation as a slave-

only device in a single or multislave, and single or multi-

master system. Slave devices can share the bus by

uniquely setting the 7-bit slave address. The 2-wire

interface consists of a serial-data line (SDA) and serial-

clock line (SCL). SDA and SCL provide bidirectional

communication between the MAX17043/MAX17044

slave device and a master device at speeds up to

400kHz. The MAX17043/MAX17044s’ SDA pin operates

bidirectionally; that is, when the MAX17043/MAX17044

receive data, SDA operates as an input, and when the

MAX17043/MAX17044 return data, SDA operates as an

open-drain output, with the host system providing a

resistive pullup. The MAX17043/MAX17044 always

operate as a slave device, receiving and transmitting

data under the control of a master device. The master

initiates all transactions on the bus and generates the

SCL signal, as well as the START and STOP bits, which

begin and end each transaction.

Bit Transfer

One data bit is transferred during each SCL clock

cycle, with the cycle defined by SCL transitioning low-

to-high and then high-to-low. The SDA logic level must

remain stable during the high period of the SCL clock

pulse. Any change in SDA when SCL is high is inter-

preted as a START or STOP control signal.

Bus Idle

The bus is defined to be idle, or not busy, when no

master device has control. Both SDA and SCL remain

high when the bus is idle. The STOP condition is the

proper method to return the bus to the idle state.

START and STOP Conditions

The master initiates transactions with a START condi-

tion (S) by forcing a high-to-low transition on SDA while

SCL is high. The master terminates a transaction with a

STOP condition (P), a low-to-high transition on SDA

while SCL is high. A Repeated START condition (Sr)

can be used in place of a STOP then START sequence

to terminate one transaction and begin another without

returning the bus to the idle state. In multimaster sys-

tems, a Repeated START allows the master to retain

control of the bus. The START and STOP conditions are

the only bus activities in which the SDA transitions

when SCL is high.

Acknowledge Bits

Each byte of a data transfer is acknowledged with an

acknowledge bit (A) or a no-acknowledge bit (N). Both

the master and the MAX17043 slave generate acknowl-

edge bits. To generate an acknowledge, the receiving

device must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and

keep it low until SCL returns low. To generate a no-

acknowledge (also called NAK), the receiver releases

SDA before the rising edge of the acknowledge-related

clock pulse and leaves SDA high until SCL returns low.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer can occur if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the bus master should reattempt

communication.

Data Order

A byte of data consists of 8 bits ordered most signifi-

cant bit (MSb) first. The least significant bit (LSb) of

each byte is followed by the acknowledge bit. The

MAX17043/MAX17044 registers composed of multibyte

values are ordered MSb first. The MSb of multibyte reg-

isters is stored on even data-memory addresses.

Slave Address

A bus master initiates communication with a slave

device by issuing a START condition followed by a

slave address (SAddr) and the read/write (R/W) bit.

When the bus is idle, the MAX17043/MAX17044 contin-

uously monitor for a START condition followed by its

slave address. When the MAX17043/MAX17044

receive a slave address that matches the value in the

slave address register, they respond with an acknowl-

edge bit during the clock period following the R/W bit.

The 7-bit slave address is fixed to 6Ch (write)/

6Dh (read):

Read/Write Bit

The R/W bit following the slave address determines the

data direction of subsequent bytes in the transfer. R/W

= 0 selects a write transaction, with the following bytes

being written by the master to the slave. R/W = 1

selects a read transaction, with the following bytes

being read from the slave by the master. (Table 5).

MAX17043/MAX17044

SLAVE ADDRESS

0110110