Single/Dual, 16ns, High Sink/Source

Current Gate Drivers

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9

Pin Description

PIN

MAX15024

MAX15025A

MAX15025B

MAX15025C

MAX15025D

NAME

FUNCTION

1

1

1

FB/SET

Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a

22

2

Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of

1µF. Input of the internal housekeeping regulator and of the main REG

regulator.

3

3

3

GND

Signal Ground

4

—

—

IN+

—

4

4

IN1

Driver 1 Noninverting Logic Input

5

—

—

IN-

Driver Inverting Logic Input. Connect to GND when not used.

—

5

—

IN2

Driver 2 Noninverting Logic Input

——

5

IN2

Driver 2 Inverting Logic Input

6

6

6

PGND

Power Ground. Sink current return. Source of the internal pulldown

n-channel transistor.

7

—

—

N_OUT

Sink Output. Open-drain n-channel output. N_OUT sinks current for power

MOSFET turn-off.

—

7

7

OUT2

Driver 2 Output

8

—

—

P_OUT

Source Output. Pullup p-channel output (open drain). Sources current for

power MOSFET turn-on.

—

8

8

OUT1

Driver 1 Output

9

9

9

DRV

Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1µF

ceramic capacitor to PGND placed in close proximity to the device. DRV

together when there is no need for special DRV supply sequencing and

the power-MOSFET gate voltage does not need to be regulated or limited.

10

10

10

REG

Voltage Regulator Output. Connect to DRV for driving the power MOSFET

ceramic capacitor to GND placed in close proximity to the device to

ensure regulator stability.

——

—

EP

Exposed Pad. Internally connected to GND. Connect to GND plane or

thermal pad and use multiple vias to a solid copper area on the bottom of

the PCB.