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19 page 
______________________________________________________________________________________ 19 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3FA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. Entering Power-Down Mode To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 8). By pulling CS high, the current conversion terminates and DOUT enters high impedance. Exiting Power-Down Mode To exit power-down mode, implement one dummy con- version by driving CS low for at least 10 clock cycles (see Figure 9). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 3Msps operation (48MHz SCLK) is 333ns. The power-up time for 2Msps operation (32MHz SCLK) is 500ns. ADC Transfer Function The output format is straight binary. The code transi- tions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size for single- channel devices is VDD/2n and for dual-channel devices is VREF/2n, where n is the resolution. The ideal transfer characteristic is shown in Figure 10. Figure 8. Entering Power-Down Mode Figure 9. Exiting Power-Down Mode Figure 10. ADC Transfer Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH IMPEDANCE INVALID DATA SCLK CS DOUT INVALID DATA OR HIGH IMPEDANCE HIGH IMPEDANCE PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE SCLK CS DOUT INVALID DATA (DUMMY CONVERSION) VALID DATA FS - 1.5 x LSB OUTPUT CODE ANALOG INPUT (LSB) 111...111 111...110 111...101 0 1 2 3 2n-2 2n-1 2n 000...000 000...001 000...010 FULL SCALE (FS): AIN1/AIN2 = REF (TDFN, µMax) AIN = VDD (SOT) n = RESOLUTION |
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