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DS2777 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS2777 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 46 page 2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication _______________________________________________________________________________________ 5 ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (DS2777/DS2778 ONLY) (VDD = +4.0V to +9.2V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 4) 0 400 kHz Bus-Free Time Between a STOP and START Condition tBUF 1.3 μs Hold Time (Repeated) START Condition tHD:STA (Note 5) 0.6 μs Low Period of SCL Clock tLOW 1.3 μs High Period of SCL Clock tHIGH 0.6 μs Setup Time for a Repeated START Condition tSU:STA 0.6 μs Data Hold Time tHD:DAT (Notes 6, 7) 0 0.9 μs Data Setup Time tSU:DAT (Note 6) 100 ns Rise Time of Both SDA and SCL Signals tR 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 μs Spike Pulse Widths Suppressed by Input Filter tSP (Note 8) 0 50 ns Capacitive Load for Each Bus Line CB (Note 9) 400 pF SCL, SDA Input Capacitance CBIN 60 pF Note 1: Accumulation bias and offset bias registers set to 00h. NBEN bit set to 0. Note 2: Measurement made with VSRC = +8V, VGS driven with external +4.5V supply. Note 3: Overvoltage (OV) and undervoltage (UV) delays (tOVD, tUVD) are reduced to zero seconds if the OV or UV condition is detected within 100ms of entering active mode. Note 4: Timing must be fast enough to prevent the DS2777/DS2778 from entering sleep mode due to bus low for period > tSLEEP. Note 5: fSCL must meet the minimum clock low time plus the rise/fall times. Note 6: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. Note 9: CB is total capacitance of one bus line in pF. |
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