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SC18IS603IPW Datasheet(PDF) 11 Page - NXP Semiconductors |
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SC18IS603IPW Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 25 page SC18IS602_602B_603_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 March 2008 11 of 25 NXP Semiconductors SC18IS602/602B/603 I2C-bus to SPI bridge A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled LOW by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin LOW under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the pin below its input threshold voltage. The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the pin HIGH. The quasi-bidirectional pin configuration is shown in Figure 16. Although the SC18IS602/602B/603 is a 3 V device, most of the pins are 5 V tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins configured in quasi-bidirectional mode is discouraged. A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression circuit. 7.1.11.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a pin configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode. The open-drain pin configuration is shown in Figure 17. An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit. Fig 16. Quasi-bidirectional output configuration 002aac548 2 SYSTEM CLOCK CYCLES weak strong very weak VDD PP P VSS pin latch data GPIO pin glitch rejection input data |
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