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SC68C752BIB48 Datasheet(PDF) 11 Page - NXP Semiconductors |
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SC68C752BIB48 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 48 page SC68C752B_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 20 January 2010 11 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.3.3 Software flow control example 6.3.3.1 Assumptions UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52. UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RX FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RX FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1 to resume transmission. Fig 7. Software flow control example TRANSMIT FIFO PARALLEL-TO-SERIAL SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD Xoff2 WORD RECEIVE FIFO PARALLEL-TO-SERIAL SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD Xoff2 WORD UART2 UART1 002aaa229 data Xoff–Xon–Xoff compare programmed Xon-Xoff characters |
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