SC16C750BIA44 datasheet(8/44 Pages) NXP

Part #	SC16C750BIA44

Description	5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

8 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

[1]

In Sleep mode, XTAL2 is left ﬂoating.

6.

Functional description

The SC16C750B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The SC16C750B is fabricated with an advanced CMOS process to achieve low

drain power and high speed requirements.

The SC16C750B is an upward solution that provides 64 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The

SC16C750B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C750B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware ﬂow control is uniquely

provided for maximum data throughput performance, especially when operating in a

multi-channel environment. The combination of the above greatly reduces the bandwidth

requirement of the external controlling CPU, increases performance, and reduces power

consumption.

The SC16C750B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input

(at 5 V).

TXRDY27

13

15

O

Transmitter ready. Transmitter DMA signaling is available with

TXRDY. When operating in the FIFO mode, one of two types of

DMA signaling can be selected using FCR[3]. When operating in

the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports

single-transfer DMA in which a transfer is made between CPU bus

cycles. Mode 1 supports multi-transfer DMA in which multiple

transfers are made continuously until the transmit FIFO has been

ﬁlled.

VCC

44

40

27

Power 2.5 V, 3 V or 5 V supply voltage.

GND

22

8

13

Power Ground voltage.

IOW

21

6

-

I

Write inputs. When either IOW or IOW is active (LOW or HIGH,

respectively) and while the UART is selected, the CPU is allowed to

write control words or data into a selected UART register. Only one

of these inputs is required to transfer data during a write operation;

the other input should be tied to its inactive level (that is, IOW tied

LOW or IOW tied HIGH).

IOW

20

4

11

I

XTAL1

18

1

9

I

Crystal connection or External clock input.

XTAL2[1]

19

2

10

O

Crystal connection or the inversion of XTAL1 if XTAL1 is

driven.

Table 2.

Pin description …continued

Symbol

Type

Description

PLCC44 LQFP64

HVQFN32

Similar Part No. - SC16C750BIA44

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	SC16C750BIA44	216Kb / 44P	5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 03-13 December 2004

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Similar Description - SC16C750BIA44

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	SC16C750B	216Kb / 44P	5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 03-13 December 2004
	SC16C751B	159Kb / 32P	5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 02-10 October 2008
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	SC16C752B	225Kb / 47P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 03-14 December 2004
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SC16C750BIA44 Datasheet(PDF) 8 Page - NXP Semiconductors

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