Si5323 datasheet(4/50 Pages) SILABS

Part #	Si5323

Description	Pin-Controlled 1_710 MHz Jitter Cleaning Clock

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Manufacturer	SILABS [Silicon Laboratories]

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Si5317

4

Preliminary Rev. 0.15

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Temperature Range

TA

–40

25

85

ºC

Supply Voltage

VDD

3.3 V nominal

2.97

3.3

3.63

V

2.5 V nominal

2.25

2.5

2.75

V

1.8 V nominal

1.71

1.8

1.89

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Supply Current (Supply

current is independent of

VDD)

IDD

LVPECL Format

622.08 MHz Out

All CKOUTs Enabled1

—

251

279

mA

LVPECL Format

622.08 MHz Out

Only 1 CKOUT Enabled1

—

217

243

mA

CMOS Format

19.44 MHz Out

All CKOUTs Enabled2

—

204

234

mA

CMOS Format

19.44 MHz Out

Only CKOUT1 Enabled2

—

194

220

mA

CKIN Input Pin

Input Common Mode

Voltage

(Input Threshold Voltage)

VICM

1.8 V ± 5%

0.9

—

1.4

V

2.5 V ± 10%

1.0

—

1.7

V

3.3 V ± 10%

1.1

—

1.95

V

Input Resistance

CKNRIN

Single-ended

20

40

60

k



Input Voltage Level Limits

CKNVIN

See note 3

0—

VDD

V

Single-ended Input Voltage

Swing

VISE

fCKIN < 212.5 MHz

See Figure 2.

0.2

—

VPP

fCKIN > 212.5 MHz

See Figure 2.

0.25

—

VPP

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

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