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PMK35EP Datasheet(PDF) 2 Page - NXP Semiconductors |
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PMK35EP Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page PMK35EP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 29 April 2010 2 of 12 NXP Semiconductors PMK35EP P-channel TrenchMOS extremely low level FET 2. Pinning information 3. Ordering information 4. Limiting values Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S source SOT96-1 (SO8) 2S source 3S source 4 G gate 5 D drain 6 D drain 7 D drain 8 D drain 4 5 1 8 G D S 001aaa025 Table 3. Ordering information Type number Package Name Description Version PMK35EP SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C ---30 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 150 °C; RGS =20 kΩ ---30 V VGS gate-source voltage -25 - 25 V ID drain current Tsp =25 °C; VGS = -10 V; see Figure 1; see Figure 3 ---14.9 A Tsp = 100 °C; VGS = -10 V; see Figure 1 ---7 A IDM peak drain current Tsp =25 °C; tp ≤ 10 µs; pulsed; see Figure 3 ---28.8 A Ptot total power dissipation Tsp =25 °C; see Figure 2 --6.9 W Tstg storage temperature -55 - 150 °C Tj junction temperature -55 - 150 °C Source-drain diode IS source current Tsp = 25 °C ---5.8 A ISM peak source current Tsp =25 °C; tp ≤ 10 µs; pulsed - - -23 A |
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