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MCIMX233CAG4B Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MCIMX233CAG4B Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 1612 page  i.MX23 Applications Processor Reference Manual, Rev. 1 vi Freescale Semiconductor Preliminary—Subject to Change Without Notice Contents Paragraph Number Title Page Number 12.2.6.6 Refresh Masking.................................................................................................. 12-16 12.2.6.7 Mobile DDR Devices .......................................................................................... 12-17 12.2.6.8 Partial Array Self-Refresh ................................................................................... 12-17 12.2.7 EMI Clock Frequency Change Requirements ......................................................... 12-17 12.3 Power Management ..................................................................................................... 12-18 12.4 AXI/AHB Port Arbitration .......................................................................................... 12-18 12.4.1 Legacy Timestamp Mode ........................................................................................ 12-19 12.4.2 Timestamp/write-priority Hybrid Mode .................................................................. 12-19 12.4.3 Port Priority Mode ................................................................................................... 12-20 12.5 Programmable Registers .............................................................................................. 12-20 12.6 EMI Memory Parameters and Register Settings.......................................................... 12-68 12.6.1 Mobile DDR (5 nsec) Parameters ............................................................................ 12-68 12.6.1.1 Bypass Cutoff ...................................................................................................... 12-68 12.6.1.2 Bypass Mode Enabled ......................................................................................... 12-68 12.6.1.3 Bypass Mode Disabled ........................................................................................ 12-69 12.6.1.4 Example Register Settings ................................................................................... 12-69 12.6.2 Mobile DDR (6 nsec)............................................................................................... 12-70 12.6.2.1 Bypass Cutoff ...................................................................................................... 12-71 12.6.2.2 Bypass Mode Enabled ......................................................................................... 12-71 12.6.2.3 Bypass Mode Disabled ........................................................................................ 12-71 12.6.2.4 Example Register Settings ................................................................................... 12-72 12.6.3 Mobile DDR (7.5 nsec)............................................................................................ 12-73 12.6.3.1 Bypass Cutoff ...................................................................................................... 12-73 12.6.3.2 Bypass Mode Enabled ......................................................................................... 12-74 12.6.3.3 Bypass Mode Disabled ........................................................................................ 12-74 12.6.3.4 Example Register Settings ................................................................................... 12-74 12.6.4 DDR ......................................................................................................................... 12-76 12.6.4.1 Bypass Mode Disabled ........................................................................................ 12-76 12.6.4.2 Example Register Settings ................................................................................... 12-77 Chapter 13 General-Purpose Media Interface (GPMI) 13.1 Overview........................................................................................................................ 13-1 13.2 GPMI NAND Flash Mode ............................................................................................. 13-2 13.2.1 Multiple NAND Flash Support.................................................................................. 13-3 13.2.2 GPMI NAND Flash Timing and Clocking ................................................................ 13-3 13.2.3 Basic NAND Flash Timing........................................................................................ 13-4 13.2.4 High-Speed NAND Flash Timing ............................................................................. 13-4 13.2.5 NAND Flash Command and Address Timing Example............................................ 13-6 13.2.6 Hardware BCH/ECC (ECC8) Interface ..................................................................... 13-6 |
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