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ADS6444IRGCR Datasheet(PDF) 11 Page - Texas Instruments |
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ADS6444IRGCR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 80 page  ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TIMING SPECIFICATIONS (1) (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. ADS6445 ADS6444 ADS6443 ADS6442 TEST Fs = 125 MSPS Fs = 105 MSPS Fs = 80 MSPS Fs = 65 MSPS PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Time for a sample to ADC Latency Clock propagate to 12 12 12 12 (7) cycles ADC outputs, see Figure 1 Time to valid data after coming out of 100 100 100 100 μs global power down Time to valid data after input Wake up time 100 100 100 100 μs clock is re-started Time to valid data after Clock coming out of 200 200 200 200 cycles channel standby tRISE Data rise From –100 mV 50 100 200 50 100 50 100 200 50 100 200 ps time to +100 mV tFALL Data fall time From +100 mV 50 100 200 50 100 50 100 200 50 100 200 ps to –100 mV Bit clock and From –100mV tRISE frame clock 50 100 200 50 100 50 100 200 50 100 200 ps to +100mV rise time Bit clock and From +100mV tFALL frame clock 50 100 200 50 100 50 100 200 50 100 200 ps to –100mV fall time LVDS Bit clock duty 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55% cycle LVDS Frame clock duty 47% 50% 53% 47% 50% 53% 47% 50% 53% 47% 50% 53% cycle (7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as shown in Table 27. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 |
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