PHKD6N02LT

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Product data sheet

Rev. 04 — 27 April 2010

2 of 13

NXP Semiconductors

PHKD6N02LT

Dual N-channel TrenchMOS logic level FET

2.

Pinning information

3.

Ordering information

4.

Limiting values

Table 2.

Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1S1

source1

SOT96-1 (SO8)

2

G1

gate1

3S2

source2

4

G2

gate2

5D2

drain2

6D2

drain2

7D1

drain1

8D1

drain1

4

5

1

8

D1

mbk725

G1

S1

D1

D2

G2

S2

D2

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PHKD6N02LT

SO8

plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

drain-source voltage

--20

V

drain-gate voltage

--20

V

gate-source voltage

-12

-

12

V

drain current

see Figure 1

--6.8

A

see Figure 1; see Figure 3

-

-

10.9

A

peak drain current

device conducting; see Figure 3

--44

A

total power dissipation

--4.17

W

storage temperature

-55

-

150

°C

junction temperature

-55

-

150

°C

Source-drain diode

source current

--3.5

A

peak source current

-

-

44

A