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PHKD6N02LT Datasheet(PDF) 2 Page - NXP Semiconductors |
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PHKD6N02LT Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 13 page PHKD6N02LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 April 2010 2 of 13 NXP Semiconductors PHKD6N02LT Dual N-channel TrenchMOS logic level FET 2. Pinning information 3. Ordering information 4. Limiting values Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S1 source1 SOT96-1 (SO8) 2 G1 gate1 3S2 source2 4 G2 gate2 5D2 drain2 6D2 drain2 7D1 drain1 8D1 drain1 4 5 1 8 D1 mbk725 G1 S1 D1 D2 G2 S2 D2 Table 3. Ordering information Type number Package Name Description Version PHKD6N02LT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C --20 V VDGR drain-gate voltage Tj ≤ 150 °C; Tj ≥ 25 °C; RGS =20kΩ --20 V VGS gate-source voltage -12 - 12 V ID drain current Tsp = 100 °C; Single device conducting; see Figure 1 --6.8 A Tsp = 25 °C; Single device conducting; see Figure 1; see Figure 3 - - 10.9 A IDM peak drain current Tsp =25 °C; tp ≤ 100 µs; pulsed; Single device conducting; see Figure 3 --44 A Ptot total power dissipation Tsp =25 °C; see Figure 2 --4.17 W Tstg storage temperature -55 - 150 °C Tj junction temperature -55 - 150 °C Source-drain diode IS source current Tsp = 25 °C --3.5 A ISM peak source current Tsp =25 °C; tp ≤ 10 µs; pulsed - - 44 A |
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