PH20100S datasheet(2/12 Pages) NXP

Part #	PH20100S

Description	N-channel TrenchMOS standard level FET

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Manufacturer	NXP [NXP Semiconductors]

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PH20100S_3

Product data sheet

Rev. 03 — 2 February 2009

2 of 12

NXP Semiconductors

PH20100S

N-channel TrenchMOS standard level FET

2.

Pinning information

3.

Ordering information

4.

Limiting values

Table 2.

Pinning information

Symbol

Description

Simplified outline

Graphic symbol

1S

source

SOT669

(LFPAK)

2S

source

3S

source

4G

gate

mb

D

mounting base; connected to

drain

mb

1234

S

D

G

mbb076

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PH20100S

LFPAK

plastic single-ended surface-mounted package (LFPAK); 4 leads

SOT669

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

VDS

drain-source voltage

Tj ≥ 25 °C; Tj ≤ 150 °C

-

100

V

VGS

gate-source voltage

-20

20

V

ID

drain current

VGS =10V; Tmb = 100 °C; see Figure 2

-21.6

A

VGS =10V; Tmb =25°C; see Figure 2;

see Figure 1

-34.3

A

IDM

peak drain current

tp ≤ 10 µs; pulsed; Tmb =25°C; see Figure 1

-137

A

Ptot

total power dissipation

Tmb =25°C

-

62.5

W

Tstg

storage temperature

-55

150

°C

Tj

junction temperature

-55

150

°C

Source-drain diode

IS

source current

Tmb =25°C

-

52

A

ISM

peak source current

tp ≤ 10 µs; pulsed; Tmb =25°C

-

137

A

Avalanche ruggedness

EDS(AL)S

non-repetitive

drain-source avalanche

energy

VGS =10V; Tj(init) =25°C; ID =12A; Vsup ≤ 100 V;

unclamped; tp =0.3 ms

-250

mJ

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