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PH1825AL Datasheet(PDF) 1 Page - NXP Semiconductors |
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PH1825AL Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 13 page PH1825AL N-channel TrenchMOS logic level FET Rev. 01 — 22 April 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits 100% gate resistance tested 100% Ruggedness tested Lead-free package Logic level compatible Optimimzed for use in DC-to-DC converters Very low switching and conduction losses 1.3 Applications DC-to-DC converters Notebook computers Switched-mode power supplies Voltage regulators 1.4 Quick reference data [1] Continuous current is limited by package. Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 25 V ID drain current Tmb =25°C; VGS =10V; see Figure 1; see Figure 3 [1] - - 100 A Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID =25A; VDS = 12 V; see Figure 12; see Figure 13 -8 -nC Static characteristics RDSon drain-source on-state resistance VGS =10V; ID =25 A; Tj = 25 °C; see Figure 10; see Figure 11 -1.4 1.8 m Ω |
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