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C8051F711-GQ Datasheet(PDF) 5 Page - Silicon Laboratories |
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C8051F711-GQ Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 290 page Rev. 0.2 5 C8051F70x/71x 20.4.1. VDD Maintenance and the VDD Monitor .............................................. 137 20.4.2. PSWE Maintenance .............................................................................. 137 20.4.3. System Clock ........................................................................................ 138 21. EEPROM ............................................................................................................... 141 21.1. RAM Reads and Writes ................................................................................. 141 21.2. Auto Increment .............................................................................................. 141 21.3. Interfacing with the EEPROM........................................................................ 141 21.4. EEPROM Security ......................................................................................... 142 22. Power Management Modes................................................................................. 146 22.1. Idle Mode....................................................................................................... 146 22.2. Stop Mode ..................................................................................................... 147 22.3. Suspend Mode .............................................................................................. 147 23. Reset Sources ...................................................................................................... 149 23.1. Power-On Reset ............................................................................................ 150 23.2. Power-Fail Reset / VDD Monitor ................................................................... 151 23.3. External Reset ............................................................................................... 152 23.4. Missing Clock Detector Reset ....................................................................... 152 23.5. Comparator0 Reset ....................................................................................... 153 23.6. Watchdog Timer Reset.................................................................................. 153 23.7. Flash Error Reset .......................................................................................... 153 23.8. Software Reset .............................................................................................. 153 24. Watchdog Timer................................................................................................... 155 24.1. Enable/Reset WDT........................................................................................ 155 24.2. Disable WDT ................................................................................................. 155 24.3. Disable WDT Lockout.................................................................................... 155 24.4. Setting WDT Interval ..................................................................................... 155 25. Oscillators and Clock Selection ......................................................................... 157 25.1. System Clock Selection................................................................................. 157 25.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 159 25.3. External Oscillator Drive Circuit..................................................................... 161 25.3.1. External Crystal Example...................................................................... 163 25.3.2. External RC Example............................................................................ 164 25.3.3. External Capacitor Example.................................................................. 165 26. Port Input/Output ................................................................................................. 166 26.1. Port I/O Modes of Operation.......................................................................... 167 26.1.1. Port Pins Configured for Analog I/O...................................................... 167 26.1.2. Port Pins Configured For Digital I/O...................................................... 167 26.1.3. Interfacing Port I/O to 5 V Logic ............................................................ 168 26.1.4. Increasing Port I/O Drive Strength ........................................................ 169 26.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 169 26.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 169 26.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 170 26.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 170 26.3. Priority Crossbar Decoder ............................................................................. 171 26.4. Port I/O Initialization ...................................................................................... 173 |
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