PCA9512A_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 19 August 2009

7 of 23

NXP Semiconductors

PCA9512A

rate is slow enough that the output catches up it will still lag the falling voltage of the input

delay and the output is still limited by its turn-on delay and the falling edge slew rate. The

output falling edge slew rate is a function of the internal maximum slew rate which is a

capacitance.

8.5 Rise time accelerators

During positive bus transactions, a 2 mA current source is switched on to quickly slew the

SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A is exceeded.

The rising edge rate should be at least 1.25 V/

µs to guarantee turn on of the accelerators.

The built-in

∆V/∆t rise time accelerators on all SDA and SCL lines requires the bus pull-up

time accelerators can be disabled through the ACC pin for lightly loaded systems.

8.6 ACC boost current enable

Users having lightly loaded systems may wish to disable the rise time accelerators.

Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn

accelerators.

8.7 Resistor pull-up value selection

The system pull-up resistors must be strong enough to provide a positive slew rate of

1.25 V/

µs on the SDAn and SCLn pins, in order to activate the boost pull-up currents

during rising edges. Choose maximum resistor value using the formula given in

Equation 1:

(1)

and C is the equivalent bus capacitance in picofarads.

requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the

card, and these pull-up values are needed to overcome the precharge voltage. See the

curves in Figure 5 and Figure 6 for guidance in resistor pull-up selection.

R

PU

800

10

()

0.6

–

C

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