PCA9512A_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 19 August 2009

4 of 23

NXP Semiconductors

PCA9512A

7.

Pinning information

7.1 Pinning

7.2 Pin description

8.

Functional description

Refer to Figure 1 “Block diagram of PCA9512A”.

8.1 Start-up

more positive or they may be equal, however the PCA9512A will not leave the

state. In the undervoltage lock out state the connection circuitry is disabled, the rise time

state; during this state the 1 V precharge circuitry is activated and pulls up the SDAn and

SCLn pins to 1 V through individual 100 k

Ω nominal resistors. At the end of the

initialization state the ‘Stop bit and bus idle’ detect circuit is enabled. When all the SDAn

and SCLn pins have been HIGH for the bus idle time or when all pins are HIGH and a

Fig 2.

Pin configuration for SO8

Fig 3.

Pin configuration for TSSOP8

SCLOUT

SDAOUT

SCLIN

SDAIN

GND

ACC

002aab789

1

2

3

4

6

5

8

7

PCA9512AD

PCA9512ADP

SCLOUT

SDAOUT

SCLIN

SDAIN

GND

ACC

002aab790

1

2

3

4

6

5

8

7

Table 3.

Pin description

Symbol

Pin

Description

1

from SDAOUT and SCLOUT to this pin.

SCLOUT

2

serial clock output to and from the SCL bus on the card

SCLIN

3

serial clock input to and from the SCL bus on the backplane

GND

4

ground supply; connect this pin to a ground plane for best results.

ACC

5

CMOS threshold digital input pin that enables and disables the rise time

accelerators on all four SDAn and SCLn pins. ACC enables all accelerators

SDAIN

6

serial data input to and from the SDA bus on the backplane

SDAOUT

7

serial data output to and from the SDA bus on the card

8

supply voltage; from the backplane, connect pull-up resistors from SDAIN

and SCLIN to this pin.