PCA9510A_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 18 August 2009

7 of 24

NXP Semiconductors

PCA9510A

8.4 Propagation delays

The delay for a rising edge is determined by the combined pull-up current from the bus

resistors and the rise time accelerator current source and the effective capacitance on the

lines. If the pull-up currents are the same, any difference in rise time is directly

negative if the output capacitance is less than the input capacitance and would be positive

if the output capacitance is larger than the input capacitance, when the currents are the

same.

maximum slew rate, and even if the input slew rate is slow enough that the output catches

occurs when the input is driven LOW with zero delay and the output is still limited by its

turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function

well as the load current and the load capacitance.

8.5 READY digital output

This pin provides a digital flag which is LOW when either ENABLE is LOW or the start-up

sequence described earlier in this section has not been completed. READY goes HIGH

when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain

pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of

10 k

Ω to V

8.6 ENABLE low current disable

Grounding the ENABLE pin disconnects the backplane side from the card side, disables

the rise time accelerators, drives READY LOW, disables the bus precharge circuitry, and

part waits for data transactions on both the backplane and card sides to be complete

before reconnecting the two sides.

8.7 Resistor pull-up value selection

The system pull-up resistors must be strong enough to provide a positive slew rate of

1.25 V/

µs on the SDAn and SCLn pins, in order to activate the boost pull-up currents

during rising edges. Choose maximum resistor value using Equation 1:

(1)

volts, and C is the equivalent bus capacitance in picofarads.

requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the

card, and these pull-up values are needed to overcome the precharge voltage. See the

curves in Figure 5 and Figure 6 for guidance in resistor pull-up selection.

R

PU

800

10

3

×

V

CC min

()

0.6

–

C

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