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S3S12HZ256J3MAL Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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S3S12HZ256J3MAL Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 692 page  MC9S12HZ256 Data Sheet, Rev. 2.05 4 Freescale Semiconductor This document contains information for all constituent modules, with the exception of the S12 CPU. For S12 CPU information please refer to the CPU S12 Reference Manual. To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision History Date Revision Level Description October 10, 2005 02.01 New Data Sheet April 20, 2006 02.02 Corrected Table 4-1 Port U and Port V descriptions Added 80QFP to PCB layout guidelines Added derivative differences to appendix D Updated ordering information on appendix E October 5, 2006 02.03 Added ROM to memory options Updated memory map figures and added tables for RAM mapping options Added ROM derivatives to appendix D Added ROM description to appendices (appendix E) October 31, 2006 02.04 Added MC3S12HZ64 mask set Updated Table A-5 Thermal Package Characteristics Updated Table A-17 PLL Characteristics April 25, 2008 02.05 Added MC3S12HZ64 Pinout. Figure 1-7 Corrected register map typo. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. |
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