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S9S08DZ128F2CLF Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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S9S08DZ128F2CLF Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 458 page  MC9S08DZ128 Series Data Sheet, Rev. 1 Freescale Semiconductor 11 Section Number Title Page Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction .........................................................................................................101 6.2 Pull-up, Slew Rate, and Drive Strength..........................................................................................102 6.3 Pin Interrupts ..................................................................................................................................103 6.3.1 Edge Only Sensitivity .....................................................................................................103 6.3.2 Edge and Level Sensitivity ..............................................................................................103 6.3.3 Pull-up/Pull-down Resistors ...........................................................................................104 6.3.4 Pin Interrupt Initialization ...............................................................................................104 6.4 Pin Behavior in Stop Modes...........................................................................................................104 6.5 Parallel I/O and Pin Control Registers ...........................................................................................104 6.5.1 Port A Registers ..............................................................................................................105 6.5.2 Port B Registers ..............................................................................................................109 6.5.3 Port C Registers ..............................................................................................................113 6.5.4 Port D Registers ..............................................................................................................116 6.5.5 Port E Registers ...............................................................................................................120 6.5.6 Port F Registers ...............................................................................................................123 6.5.7 Port G Registers ..............................................................................................................126 6.5.8 Port H Registers ..............................................................................................................129 6.5.9 Port J Registers ...............................................................................................................132 6.5.10 Port K Registers ..............................................................................................................136 6.5.11 Port L Registers ...............................................................................................................139 Chapter 7 Central Processor Unit (S08CPUV5) 7.1 Introduction ....................................................................................................................................143 7.1.1 Features ...........................................................................................................................143 7.2 Programmer’s Model and CPU Registers ......................................................................................144 7.2.1 Accumulator (A) .............................................................................................................144 7.2.2 Index Register (H:X) .......................................................................................................144 7.2.3 Stack Pointer (SP) ...........................................................................................................145 7.2.4 Program Counter (PC) ....................................................................................................145 7.2.5 Condition Code Register (CCR) .....................................................................................145 7.3 Addressing Modes..........................................................................................................................147 7.3.1 Inherent Addressing Mode (INH) ...................................................................................147 7.3.2 Relative Addressing Mode (REL) ...................................................................................147 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................147 7.3.4 Direct Addressing Mode (DIR) ......................................................................................148 7.3.5 Extended Addressing Mode (EXT) ................................................................................148 7.3.6 Indexed Addressing Mode ..............................................................................................148 7.4 Special Operations..........................................................................................................................149 7.4.1 Reset Sequence ...............................................................................................................149 |
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