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MC9S08JM16CGTE Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC9S08JM16CGTE Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 386 page  MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor 11 6.2 Port Data and Data Direction ..........................................................................................................78 6.3 Pin Control ......................................................................................................................................79 6.3.1 Internal Pullup Enable ......................................................................................................79 6.3.2 Output Slew Rate Control Enable .....................................................................................79 6.3.3 Output Drive Strength Select ............................................................................................79 6.4 Pin Behavior in Stop Modes ............................................................................................................79 6.5 Parallel I/O and Pin Control Registers ............................................................................................80 6.5.1 Port A I/O Registers (PTAD and PTADD) ........................................................................80 6.5.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................81 6.5.3 Port B I/O Registers (PTBD and PTBDD) ........................................................................82 6.5.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................83 6.5.5 Port C I/O Registers (PTCD and PTCDD) ........................................................................84 6.5.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) .................................................85 6.5.7 Port D I/O Registers (PTDD and PTDDD) .......................................................................87 6.5.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) ................................................88 6.5.9 Port E I/O Registers (PTED and PTEDD) ........................................................................89 6.5.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ..................................................91 6.5.11 Port F I/O Registers (PTFD and PTFDD) .........................................................................92 6.5.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ...................................................93 6.5.13 Port G I/O Registers (PTGD and PTGDD) .......................................................................95 6.5.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ................................................96 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction .....................................................................................................................................99 7.1.1 Features .............................................................................................................................99 7.2 Programmer’s Model and CPU Registers .....................................................................................100 7.2.1 Accumulator (A) .............................................................................................................100 7.2.2 Index Register (H:X) ......................................................................................................100 7.2.3 Stack Pointer (SP) ...........................................................................................................101 7.2.4 Program Counter (PC) ....................................................................................................101 7.2.5 Condition Code Register (CCR) .....................................................................................101 7.3 Addressing Modes .........................................................................................................................103 7.3.1 Inherent Addressing Mode (INH) ...................................................................................103 7.3.2 Relative Addressing Mode (REL) ..................................................................................103 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................103 7.3.4 Direct Addressing Mode (DIR) ......................................................................................103 7.3.5 Extended Addressing Mode (EXT) ................................................................................104 7.3.6 Indexed Addressing Mode ..............................................................................................104 7.4 Special Operations .........................................................................................................................105 7.4.1 Reset Sequence ...............................................................................................................105 7.4.2 Interrupt Sequence ..........................................................................................................105 7.4.3 Wait Mode Operation ......................................................................................................106 7.4.4 Stop Mode Operation ......................................................................................................106 7.4.5 BGND Instruction ...........................................................................................................107 |
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