EP80579 datasheet(4/1916 Pages) INTEL

Part #	EP80579

Description	Intel짰 EP80579 Integrated Processor Product Line

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Manufacturer	INTEL [Intel Corporation]

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Contents

Intel® EP80579 Integrated Processor Product Line Datasheet

August 2009

4

Order Number: 320066-003US

Contents

Introduction and Overview, Volume 1 of 6 ................................... 91

1.0

Introduction ............................................................................................................93

1.1

Introduction......................................................................................................93

1.2

Document Organization ......................................................................................93

1.3

Referenced Documents and Related Websites ........................................................94

1.4

Acronyms .........................................................................................................95

1.5

Glossary ...........................................................................................................98

2.0

Architectural Overview ..........................................................................................103

2.1

Overview ........................................................................................................ 103

2.1.1

Block Summary ......................................................................................103

2.1.2

External Interfaces ................................................................................. 106

2.1.3

Frequencies and Gear Ratios .................................................................... 107

2.2

Signaling Architecture ......................................................................................107

2.3

DMA and Peer-to-Peer Data Transfers................................................................. 109

3.0

Platform Memory and Device Configuration ........................................................... 111

3.1

Overview ........................................................................................................ 111

3.1.1

Configuration Objectives.......................................................................... 111

3.1.2

Terminology and Conventions .................................................................. 112

3.2

IA Platform Infrastructure ................................................................................. 113

3.2.1

IA Platform View of Endianness ................................................................ 113

3.2.2

IA Platform View of Configuration ............................................................. 114

3.3

High-Level Views ............................................................................................. 116

3.3.1

Characteristics of External System Memory (DRAM) .................................... 116

3.3.2

Characteristics of Internal and External Memories ....................................... 117

3.3.3

Characteristics of Device Configuration ...................................................... 118

3.4

Memory Map for IA-Attached Agents .................................................................. 119

3.5

Memory Map for AIOC-Attached Devices ............................................................. 119

3.6

Endianness .....................................................................................................119

3.7

PCI Configuration............................................................................................. 119

3.7.1

Overview............................................................................................... 120

3.7.2

Device Tree ........................................................................................... 121

3.7.3

Materializing Device Structures................................................................. 124

3.7.4

PCI Configuration Headers .......................................................................124

4.0

Signaling................................................................................................................ 131

4.1

Overview ........................................................................................................ 131

4.1.1

Terminology and Conventions .................................................................. 132

4.2

Existing Signaling Capabilities............................................................................ 132

4.2.1

IA-32 core/Platform ................................................................................ 133

4.2.1.1

MSI and INTx Signaling.................................................................... 133

4.2.1.2

GPIO Signaling ............................................................................... 133

4.2.2

Other Agents ......................................................................................... 133

4.3

Inter-Agent Signaling ....................................................................................... 134

4.3.1

Signaling that Travels Around the Signal Bridge .......................................... 135

4.3.2

Signaling that is Bridged from a Side-Band Source Signal ............................ 135

4.3.2.1

Targeting the IA-32 core with a Bridged Signal.................................... 136

5.0

Error Handling ....................................................................................................... 139

5.1

Overview ........................................................................................................ 139

5.2

EP80579 View of Error Reporting .......................................................................139

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