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FSEZ1317 Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FSEZ1317 Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 17 page  © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FSEZ1317 • Rev. 1.0.4 11 Cable Voltage Drop Compensation In cellular phone charger applications, the battery is located at the end of cable, which typically causes several percentage of voltage drop on the battery voltage. FSEZ1317 has a built-in cable voltage drop compensation that provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of the voltage regulation error amplifier. Operating Current The FSEZ1317 operating current is as small as 2.5mA, which results in higher efficiency and reduces the VDD hold-up capacitance requirement. Once FSEZ1317 enters “deep” green mode, the operating current is reduced to 0.95mA, assisting the power supply in meeting power conservation requirements. Green-Mode Operation The FSEZ1317 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency as shown in Figure 26. The switching frequency decreases as the load decreases. In heavy load conditions, the switching frequency is fixed at 50kHz. Once VCOMV decreases below 2.5V, the PWM frequency linearly decreases from 50kHz. When FSEZ1317 enters deep green mode, the PWM frequency is reduced to a minimum frequency of 370Hz, thus gaining power saving to meet international power conservation requirements. Figure 26. Switching Frequency in Green Mode Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FSEZ1317 has an internal frequency hopping circuit that changes the switching frequency between 47kHz and 53kHz over the period shown in Figure 27. Figure 27. Frequency Hopping High-Voltage Startup Figure 28 shows the HV-startup circuit for FSEZ1317 applications. The HV pin is connected to the line input or bulk capacitor through a resistor, RSTART (100kΩ recommended). During startup status, the internal startup circuit is enabled. Meanwhile, line input supplies the current, ISTARTUP, to charge the hold-up capacitor, CDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal startup circuit is disabled, blocking ISTARTUP from flowing into the HV pin. Once the IC turns on, CDD is the only energy source to supply the IC consumption current before the PWM starts to switch. Thus, CDD must be large enough to prevent VDD from dropping down to VDD-OFF before the power can be delivered from the auxiliary winding. 1 8 7 5 2 3 4 Figure 28. HV Startup Circuit |
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