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TPS54291PWP Datasheet(PDF) 11 Page - Texas Instruments |
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TPS54291PWP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 33 page TPS5429x ENx C R + PVDD2 PVDDx 10 mA (max) 1.25 V UDG-09125 X Time t DELAY 0 t DELAY + t SS PVDDx ENxB V OUTx 1.25-V Threshold TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 Figure 12. Startup Delay Schematic Figure 13. Startup Delay Timing Diagram NOTE If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to GND. This allows the outputs to “start” immediately on the valid application of PVDD2. If ENx is allowed to go “high” after the outputx has been in regulation, the upper and lower MOSFETs shut off, and the output decays at a rate determined by the output capacitor and the load. SOFT START Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of the two non-inverting inputs of the error amplifier. The other input is the internal precise 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 5.2 ms, 2.6 ms and 1.3 ms for TPS54190/1/2 respectively. During a soft start interval, the TPS5429x output slowly increases the voltage to the non-inverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the non-inverting input to the error amplifier reaches the internal 0.8V reference voltage. At that time, the voltage at the non-inverting input to the error amplifier remains at the reference voltage. During the soft-start interval, pulse-by-pulse current limiting is in effect. If an over-current pulse is detected, six PWM pulses is skipped to allow the inductor current to decay before another PWM pulse is applied (See Output Overload Protection). There is no pulse skipping if a current limit pulse is not detected. If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time soft-start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :TPS54290 TPS54291 TPS54292 |
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