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KSZ8873MLL Datasheet(PDF) 11 Page - Micrel Semiconductor |
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KSZ8873MLL Datasheet(HTML) 11 Page - Micrel Semiconductor |
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11 / 103 page  Micrel, Inc. KSZ8873MLL/FLL/RLL September 2009 11 M9999-092309-1.2 Pin Description and I/O Assignment Pin Number Pin Name Type (1) Description 1 RXM1 I/O Physical receive or transmit signal (– differential) 2 RXP1 I/O Physical receive or transmit signal (+ differential) 3 AGND Gnd Analog ground 4 TXM1 I/O Physical transmit or receive signal (– differential) 5 TXP1 I/O Physical transmit or receive signal (+ differential) 6 VDDA_3.3 P 3.3V analog VDD 7 AGND Gnd Analog ground. 8 ISET O Set physical transmit output current. Pull-down this pin with a 11.8K 1% resistor to ground. 9 VDDA_1.8 P 1.8 analog VDD input power supply from VDDCO (pin 56) through external Ferrite bead and capacitor. 10 RXM2 I/O Physical receive or transmit signal (– differential) 11 RXP2 I/O Physical receive or transmit signal (+ differential) 12 AGND Gnd Analog ground. 13 TXM2 I/O Physical transmit or receive signal (– differential) 14 TXP2 I/O Physical transmit or receive signal (+ differential) 15 FXSD2 I MLL/RLL: connect to analog ground. FLL: Fiber signal detect / factory test pin 16 PWRND Ipu Chip power down input (active low). 17 X1 I 18 X2 O 25 or 50MHz crystal/oscillator clock connections. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock is +/- 50ppm for both crystal and oscillator. 19 SMTXEN3 I Switch MII transmit enable 20 SMTXD33/ EN_REFCLKO_3 lpu/I MLL/FLL: Switch MII transmit data bit 3 RLL: Strap option: RMII mode Clock selection PU = Enable REFCLKO_3 output PD = Disable REFCLKO_3 output 21 SMTXD32/ NC I MLL/FLL: Switch MII transmit data bit 2 RLL: No connection 22 SMTXD31 I Switch MII transmit data bit 1 23 SMTXD30 I Switch MII transmit data bit 0 24 GND Gnd Digital ground 25 VDDIO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors. 26 SMTXC3/ REFCLKI_3 I/O MLL/FLL: Switch MII transmit clock (MII modes only) Output in PHY MII mode and SNI mode Input in MAC MII and RMII mode. RLL: Reference clock input Note: pull up or down is needed if internal reference clock is used in RLL. 27 SMTXER3/ MII_LINK_3 I Switch MII transmit error in MII MAC mode MII link indicator from host in MII PHY mode. High = No link. |
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