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KSZ8873MLL Datasheet(PDF) 10 Page - Micrel Semiconductor |
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KSZ8873MLL Datasheet(HTML) 10 Page - Micrel Semiconductor |
10 / 103 page Micrel, Inc. KSZ8873MLL/FLL/RLL September 2009 10 M9999-092309-1.2 List of Tables Table 1. FX Signal Threshold.........................................................................................................................................18 Table 2. MDI/MDI-X Pin Definitions ...............................................................................................................................18 Table 3. Internal Function Block Status ..........................................................................................................................23 Table 4. MII Signals .......................................................................................................................................................28 Table 5. RMII Clock Setting ............................................................................................................................................29 Table 6. RMII Signal Description....................................................................................................................................30 Table 7. RMII Signal Connections..................................................................................................................................30 Table 8. MII Management Interface Frame Format .......................................................................................................31 Table 9. Serial Management Interface (SMI) Frame Format .........................................................................................31 Table 10. FID+DA Lookup in VLAN Mode .....................................................................................................................32 Table 11. FID+SA Lookup in VLAN Mode .....................................................................................................................32 Table 12. Spanning Tree States ....................................................................................................................................34 Table 13. SPI Connections ............................................................................................................................................39 Table 14. Data Rate Limit Table ....................................................................................................................................61 Table 15. Format of Static MAC Table (8 Entries) .........................................................................................................81 Table 16. Format of Static VLAN Table (16 Entries)......................................................................................................83 Table 17. Format of Dynamic MAC Address Table (1K Entries) ...................................................................................84 Table 18. Format of “Per Port” MIB Counters ................................................................................................................85 Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets............................................................................86 Table 20. Format of “All Port Dropped Packet” MIB Counters.......................................................................................86 Table 21. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets................................................................87 Table 22. EEPROM Timing Parameters ........................................................................................................................90 Table 23. MAC Mode MII Timing Parameters................................................................................................................91 Table 24. PHY Mode MII Timing Parameters ................................................................................................................92 Table 25. RMII Timing Parameters ................................................................................................................................93 Table 26. I2C Timing Parameters ..................................................................................................................................95 Table 27. SPI Input Timing Parameters.........................................................................................................................96 Table 28. SPI Output Timing Parameters ......................................................................................................................97 Table 29. Auto-Negotiation Timing Parameters.............................................................................................................98 Table 30. Reset Timing Parameters ..............................................................................................................................99 Table 31. Transformer Selection Criteria .....................................................................................................................101 Table 32. Qualified Single Port Magnetics...................................................................................................................101 Table 33. Typical Reference Crystal Characteristics ...................................................................................................101 |
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