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KSZ8873MLL Datasheet(PDF) 9 Page - Micrel Semiconductor |
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KSZ8873MLL Datasheet(HTML) 9 Page - Micrel Semiconductor |
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9 / 103 page  Micrel, Inc. KSZ8873MLL/FLL/RLL September 2009 9 M9999-092309-1.2 List of Figures Figure 1. Typical Straight Cable Connection .................................................................................................................19 Figure 2. Typical Crossover Cable Connection .............................................................................................................20 Figure 3. Auto-Negotiation and Parallel Operation ........................................................................................................21 Figure 4. Destination Address Lookup Flow Chart, Stage 1 ..........................................................................................25 Figure 5. Destination Address Resolution Flow Chart, Stage 2.....................................................................................26 Figure 6. 802.1p Priority Field Format ...........................................................................................................................33 Figure 7. Tail Tag Frame Format ...................................................................................................................................35 Figure 8. Tail Tag Rules.................................................................................................................................................36 Figure 9. EEPROM Configuration Timing Diagram .......................................................................................................38 Figure 10. SPI Write Data Cycle ....................................................................................................................................40 Figure 11. SPI Read Data Cycle ....................................................................................................................................40 Figure 12. SPI Multiple Write .........................................................................................................................................40 Figure 13. SPI Multiple Read .........................................................................................................................................41 Figure 14. Far-End Loopback Path ................................................................................................................................42 Figure 15. Near-end (Remote) Loopback Path..............................................................................................................43 Figure 16. EEPROM Interface Input Timing Diagram....................................................................................................90 Figure 17. EEPROM Interface Output Timing Diagram .................................................................................................90 Figure 18. MAC Mode MII Timing – Data Received from MII ........................................................................................91 Figure 19. MAC Mode MII Timing – Data Transmitted to MII .......................................................................................91 Figure 20. PHY Mode MII Timing – Data Received from MII.........................................................................................92 Figure 21. PHY Mode MII Timing – Data Transmitted to MII .........................................................................................92 Figure 22. RMII Timing – Data Received from RMII ......................................................................................................93 Figure 23. RMII Timing – Data Transmitted to RMII ......................................................................................................93 Figure 24. I2C Input Timing............................................................................................................................................94 Figure 25. I2C Start Bit Timing.......................................................................................................................................94 Figure 26. I2C Stop Bit Timing .......................................................................................................................................94 Figure 27. I2C Output Timing.........................................................................................................................................94 Figure 28. SPI Input Timing ...........................................................................................................................................96 Figure 29. SPI Output Timing.........................................................................................................................................97 Figure 30. Auto-Negotiation Timing ...............................................................................................................................98 Figure 31. Reset Timing.................................................................................................................................................99 Figure 32. Recommended Reset Circuit ......................................................................................................................100 Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output..............................................100 Figure 34. 64-Pin LQFP Package ................................................................................................................................103 |
Similar Part No. - KSZ8873MLL_09 |
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Similar Description - KSZ8873MLL_09 |
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