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DAC5681IRGCT Datasheet(PDF) 4 Page - Texas Instruments |
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DAC5681IRGCT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 47 page  DAC5681 SLLS864A – AUGUST 2007 – REVISED JANUARY 2009 ................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See the “DLL Operation” section. For proper external termination, connect a 100 Ω resistor across LVDS DCLKP 25 I clock source lines followed by series 0.01 µF capacitors connected to each of DCLKP and DCLKN pins (see Figure 17). For best performance, the resistor and capacitors should be placed as close as possible to these pins. DCLKN 26 I LVDS negative input clock. (See the DCLKP description) 10, 39, 50, Digital supply voltage. (1.8 V) DVDD I 63 Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). EXTIO 56 I/O Used as 1.2V internal reference output when EXTLO = GND, requires a 0.1 µF decoupling capacitor to AGND when used as reference output. EXTLO 58 O Connect to GND for internal reference, or AVDD for external reference. 4, Thermal Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and GND I Pad IOVDD supplies. DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current IOUTA1 52 O sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described IOUTA2 53 O above. An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin. IOVDD 9 I Digital I/O supply voltage (3.3V) for pins RESETB, SCLK, SDENB, SDIO, SDO. NC 64 I No Connect. Leave open for proper operation. RESETB 49 I Resets the chip when low. Internal pull-up. SCLK 47 I Serial interface clock. Internal pull-down. SDENB 48 I Active low serial data enable, always an input to the DAC5681. Internal pull-up. Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO 46 I/O SDIO pin is an input only. Internal pull-down. Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state SDO 45 O in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14 SDO_func_sel(2:0). Internal pull-down. LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100 Ω termination resistor. By SYNCP 5 I default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N Operation paragraph for a detailed description. SYNCN 6 I LVDS SYNC negative input data. Digital supply voltage. (1.8V) Connect to DVDD pins for normal operation. This supply pin is also used VFUSE 44 I for factory fuse programming. 4 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681 |
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