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ADS8332IBPWR Datasheet(PDF) 11 Page - Texas Instruments |
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ADS8332IBPWR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 40 page ADS8331 ADS8332 www.ti.com SBAS363 – DECEMBER 2009 ADS8331 PIN DESCRIPTIONS PIN NO. NAME TSSOP QFN I/O DESCRIPTION ADCIN 21 18 I ADC input AGND 20 17 – Analog ground DGND 14 11 – Digital interface ground COM 23 20 I Common ADC input (usually connected to AGND) CONVST 15 12 I Conversion start. Freezes sample and hold, starts conversion. Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after EOC/INT/CDI 9 6 O/O/I the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode. FS/CS 11 8 I Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI. IN[0:3] 1-3, 24 21-24 I Mux inputs NC 4-7 1-4 – No connection MUXOUT 22 19 O Mux output REF+ 18 15 I External reference input External reference ground (connect to AGND through an individual via on the printed circuit REF– 19 16 – board) RESET 8 5 I External reset (active low) SCLK 10 7 I SPI clock for serial interface SDI 12 9 I SPI serial data in SDO 13 10 O SPI serial data out VA 17 14 – Analog supply, +2.7V to +5.5V VBD 16 13 – Digital interface supply ADS8332 PIN DESCRIPTIONS PIN NO. NAME TSSOP QFN I/O DESCRIPTION ADCIN 21 18 I ADC input AGND 20 17 – Analog ground DGND 14 11 – Digital interface ground COM 23 20 I Common ADC input (usually connected to AGND) CONVST 15 12 I Conversion start. Freezes sample and hold, starts conversion. Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after EOC/INT/CDI 9 6 O/O/I the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode. FS/CS 11 8 I Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI. IN[0:7] 1-7, 24 1-4, Mux inputs I 21-24 MUXOUT 22 19 O Mux output REF+ 18 15 I External reference input External reference ground (connect to AGND through an individual via on the printed circuit REF– 19 16 – board) RESET 8 5 I External reset (active low) SCLK 10 7 I SPI clock for serial interface SDI 12 9 I SPI serial data in SDO 13 10 O SPI serial data out VA 17 14 – Analog supply, +2.7 V to +5.5 V VBD 16 13 – Digital interface supply Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS8331 ADS8332 |
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