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CBTL06122AHF Datasheet(PDF) 11 Page - NXP Semiconductors |
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CBTL06122AHF Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 19 page CBTL06122_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 16 April 2009 11 of 19 NXP Semiconductors CBTL06122 High-performance DP/PCIe Gen2 hex display multiplexer 10. Characteristics 10.1 General characteristics 10.2 DisplayPort channel characteristics 10.3 AUX and DDC ports [1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time. Table 8. General characteristics Symbol Parameter Conditions Min Typ Max Unit IDD supply current operating mode (XSD = HIGH); VDD = 3.3 V - 0.2 1 mA shutdown mode (XSD = LOW); VDD = 3.3 V - - 10 µA Ptot total power dissipation operating mode (XSD = HIGH); VDD = 3.3 V - - 5 mW tstartup start-up time supply voltage valid or XSD going HIGH to channel specified operating characteristics --1 ms trcfg reconfiguration time SEL state change to channel specified operating characteristics --1 ms Table 9. DisplayPort channel characteristics Symbol Parameter Conditions Min Typ Max Unit VI input voltage −0.3 - +2.6 V VIC common-mode input voltage 0 - 2.0 V VID differential input voltage −1.2 - +1.2 V DDIL differential insertion loss channel is on; 0 Hz ≤ f ≤ 1.0 GHz −2.5 −1.6 - dB channel is on; f = 2.5 GHz −4.5 - - dB channel is off; 0 Hz ≤ f ≤ 3.0 GHz - - −20 dB DDRL differential return loss channel is on; 0 Hz ≤ f ≤ 1.0 GHz - - −10 dB DDNEXT differential near-end crosstalk adjacent channels are on; 0Hz ≤ f ≤ 1.0 GHz -- −30 dB B bandwidth −3.0 dB intercept - 2.5 - GHz −5.0 dB intercept - 4.0 - GHz tPD propagation delay from left-side port to right-side port or vice versa - 180 - ps tsk(dif) differential skew time intra-pair - - 5 ps tsk skew time inter-pair - - 180 ps Table 10. AUX and DDC port characteristics Symbol Parameter Conditions Min Typ Max Unit VI input voltage DDC or AUX −0.3 - +2.6 V VIC common-mode input voltage DDC or AUX 0 - 2.0 V VID differential input voltage −1.2 - +1.2 V tPD propagation delay from left-side port to right-side port or vice versa [1] - 180 - ps |
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