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ISO721DUBR Datasheet(PDF) 8 Page - Texas Instruments |
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ISO721DUBR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 26 page  ISO721, ISO721M ISO722, ISO722M SLLS629I – JANUARY 2006 – REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.3 0.5 ICC1 VCC1 supply current VI = VCC or 0 V, No load mA 25 Mbps 1 2 ISO722/722M EN at VCC 150 mA Sleep Mode VI = VCC or 0 V, No load ICC2 VCC2 supply current EN at 0 V or Quiescent 4 6.5 ISO721/721M mA 25 Mbps VI = VCC or 0 V, No load 5 7.5 IOH = –4 mA, See Figure 1 VCC – 0.4 3 VOH High-level output voltage V IOH = –20 mA, See Figure 1 VCC – 0.1 3.3 IOL = 4 mA, See Figure 1 0.2 0.4 VOL Low-level output voltage V IOL = 20 mA, See Figure 1 0 0.1 VI(HYS) Input voltage hysteresis 150 mV IIH High-level input current EN, IN at 2 V 10 mA IIL Low-level input current EN, IN at 0.8 V –10 High-impedance output IOZ ISO722, ISO722M EN, IN at VCC 1 mA current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6pt) 1 pF CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 25 40 kV/ms (1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay, low-to-high-level output 17 20 34 tPHL Propagation delay , high-to-low-level output ISO72x 17 20 34 ns tsk(p) Pulse skew |tPHL – tPLH| 0.5 3 EN at 0 V, See Figure 1 tPLH Propagation delay, low-to-high-level output 10 12 25 tPHL Propagation delay, high-to-low-level output ISO72xM 10 12 25 tsk(p) Pulse skew |tPHL – tPLH| 0.5 1 tsk(pp) (1) Part-to-part skew 0 5 ns tr Output signal rise time 2 EN at 0 V, ns See Figure 1 tf Output signal fall time 2 Sleep-mode propagation delay, tpHZ 7 13 25 ns high-level-to-high-mpedance output See Figure 2 Sleep-mode propagation delay, tpZH 5 6 8 µs high-impedance-to-high-level output ISO722 ISO722M Sleep-mode propagation delay, tpLZ 7 13 25 ns low-level-to-high-impedance output See Figure 3 Sleep-mode propagation delay, tpZL 5 6 8 ms high-impedance-to-low-level output tfs Failsafe output delay time from input power loss See Figure 4 3 ms 100 Mbps NRZ data input, See Figure 6 2 ISO72x 100 Mbps unrestricted bit run length data 3 input, See Figure 6 tjit(PP) Peak-to-peak eye-pattern jitter ns 150 Mbps NRZ data input, See Figure 6 1 ISO72xM 150 Mbps unrestricted bit run length data 2 input, See Figure 6 (1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 8 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M |
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