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PSMN1R5-25YL Datasheet(PDF) 2 Page - NXP Semiconductors |
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PSMN1R5-25YL Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 13 page PSMN1R5-25YL_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 16 June 2009 2 of 13 NXP Semiconductors PSMN1R5-25YL N-channel TrenchMOS logic level FET 2. Pinning information 3. Ordering information 4. Limiting values [1] Continuous current is limited by package. Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S source SOT669 (LFPAK) 2S source 3S source 4G gate mb D mounting base; connected to drain mb 1234 S D G mbb076 Table 3. Ordering information Type number Package Name Description Version PSMN1R5-25YL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 25 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 150 °C; RGS =20kΩ -25 V VGS gate-source voltage -20 20 V ID drain current VGS =10V; Tmb = 100 °C; see Figure 1 [1] -100 A VGS =10V; Tmb =25°C; see Figure 1 [1] -100 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb =25°C; see Figure 3 -815 A Ptot total power dissipation Tmb =25°C; see Figure 2 -109 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tmb =25°C; [1] -100 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb =25°C - 815 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS =10V; Tj(init) =25°C; ID =100 A; Vsup ≤ 25 V; RGS =50 Ω; unclamped -290 mJ |
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