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LM3S6730-IBZ25-A2 Datasheet(PDF) 7 Page - Texas Instruments |
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LM3S6730-IBZ25-A2 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 441 page List of Figures Figure 1-1. Stellaris ® LM3S6730 Microcontroller High-Level Block Diagram ............................. 30 Figure 2-1. CPU Block Diagram ............................................................................................. 37 Figure 2-2. TPIU Block Diagram ............................................................................................ 38 Figure 5-1. JTAG Module Block Diagram ................................................................................ 48 Figure 5-2. Test Access Port State Machine ........................................................................... 51 Figure 5-3. IDCODE Register Format ..................................................................................... 57 Figure 5-4. BYPASS Register Format .................................................................................... 57 Figure 5-5. Boundary Scan Register Format ........................................................................... 58 Figure 6-1. Basic RST Configuration ...................................................................................... 60 Figure 6-2. External Circuitry to Extend Power-On Reset ........................................................ 61 Figure 6-3. Reset Circuit Controlled by Switch ........................................................................ 61 Figure 6-4. Power Architecture .............................................................................................. 63 Figure 6-5. Main Clock Tree .................................................................................................. 65 Figure 7-1. Flash Block Diagram .......................................................................................... 116 Figure 8-1. GPIO Port Block Diagram ................................................................................... 142 Figure 8-2. GPIODATA Write Example ................................................................................. 143 Figure 8-3. GPIODATA Read Example ................................................................................. 143 Figure 9-1. GPTM Module Block Diagram ............................................................................ 183 Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 187 Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 188 Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 189 Figure 10-1. WDT Module Block Diagram .............................................................................. 219 Figure 11-1. UART Module Block Diagram ............................................................................. 243 Figure 11-2. UART Character Frame ..................................................................................... 244 Figure 11-3. IrDA Data Modulation ......................................................................................... 246 Figure 12-1. SSI Module Block Diagram ................................................................................. 283 Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 286 Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 286 Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 287 Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 287 Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 288 Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 289 Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 289 Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 290 Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 291 Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 292 Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 292 Figure 13-1. Ethernet Controller ............................................................................................. 321 Figure 13-2. Ethernet Controller Block Diagram ...................................................................... 321 Figure 13-3. Ethernet Frame ................................................................................................. 322 Figure 13-4. Interface to an Ethernet Jack .............................................................................. 327 Figure 14-1. Analog Comparator Module Block Diagram ......................................................... 367 Figure 14-2. Structure of Comparator Unit .............................................................................. 368 Figure 14-3. Comparator Internal Reference Structure ............................................................ 369 Figure 15-1. 100-Pin LQFP Package Pin Diagram .................................................................. 378 Figure 15-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 379 7 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller |
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