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LM3S6730-IQN50-A2T Datasheet(PDF) 3 Page - Texas Instruments |
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LM3S6730-IQN50-A2T Datasheet(HTML) 3 Page - Texas Instruments |
3 / 441 page Table of Contents Revision History ............................................................................................................................. 16 About This Document .................................................................................................................... 20 Audience .............................................................................................................................................. 20 About This Manual ................................................................................................................................ 20 Related Documents ............................................................................................................................... 20 Documentation Conventions .................................................................................................................. 20 1 Architectural Overview .......................................................................................... 23 1.1 Product Features .......................................................................................................... 23 1.2 Target Applications ........................................................................................................ 29 1.3 High-Level Block Diagram ............................................................................................. 29 1.4 Functional Overview ...................................................................................................... 31 1.4.1 ARM Cortex™-M3 ......................................................................................................... 31 1.4.2 Motor Control Peripherals .............................................................................................. 31 1.4.3 Analog Peripherals ........................................................................................................ 32 1.4.4 Serial Communications Peripherals ................................................................................ 32 1.4.5 System Peripherals ....................................................................................................... 33 1.4.6 Memory Peripherals ...................................................................................................... 34 1.4.7 Additional Features ....................................................................................................... 35 1.4.8 Hardware Details .......................................................................................................... 35 2 ARM Cortex-M3 Processor Core ........................................................................... 36 2.1 Block Diagram .............................................................................................................. 37 2.2 Functional Description ................................................................................................... 37 2.2.1 Serial Wire and JTAG Debug ......................................................................................... 37 2.2.2 Embedded Trace Macrocell (ETM) ................................................................................. 38 2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 38 2.2.4 ROM Table ................................................................................................................... 38 2.2.5 Memory Protection Unit (MPU) ....................................................................................... 38 2.2.6 Nested Vectored Interrupt Controller (NVIC) .................................................................... 38 3 Memory Map ........................................................................................................... 42 4 Interrupts ................................................................................................................. 44 5 JTAG Interface ........................................................................................................ 47 5.1 Block Diagram .............................................................................................................. 48 5.2 Functional Description ................................................................................................... 48 5.2.1 JTAG Interface Pins ...................................................................................................... 48 5.2.2 JTAG TAP Controller ..................................................................................................... 50 5.2.3 Shift Registers .............................................................................................................. 51 5.2.4 Operational Considerations ............................................................................................ 51 5.3 Initialization and Configuration ....................................................................................... 54 5.4 Register Descriptions .................................................................................................... 54 5.4.1 Instruction Register (IR) ................................................................................................. 54 5.4.2 Data Registers .............................................................................................................. 56 6 System Control ....................................................................................................... 59 6.1 Functional Description ................................................................................................... 59 6.1.1 Device Identification ...................................................................................................... 59 3 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller |
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