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SFSL5.5MDB Datasheet(PDF) 7 Page - Yamar Electronics Ltd. |
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SFSL5.5MDB Datasheet(HTML) 7 Page - Yamar Electronics Ltd. |
7 / 12 page Proprietary and Confidential Information of YAMAR Electronics Ltd. @ 2007 Yamar Electronics Ltd. 7 DS-SIG40 R1.8 4 OPERATION 4.1 Message Construction The host constructs a message from bytes of data sent to its UART. The device receives this data on its HDI data-In line. The 1 st low input bit (start bit) starts the signaling transmission, and the 10th high bit (stop bit) stops the transmission. If all bits, including the 10 th bit, are low, the transmission continues until a bit becomes high, but no more than 31-bit duration. It is considered as the Synch_Break Field of the LIN protocol. The stop bit stops the transmission unless a new byte is received from host. The total byte length does not change. The data latency between transmitter and receiver is about four bits. 4.1.1 LIN Protocol Messages In order to comply with the LIN protocol, transmission of two kinds of bytes are allowed: 1. Bytes beginning with a start bit, followed by 8 bits and ending with a stop bit. 2. Bytes beginning with a start bit followed by a number of zeros ranging from 9 to 30 bits and ending with a stop bit. 4.1.2 Commanding the SIG40 Writing and reading to/from the internal Control registers (See 4.2) using write and read commands set the device behavior. The registers are set by power-up Reset to operate at 19.2KBps, F0 = 5.5Mhz and F1 = 6.5Mhz. Writing into the registers allows changing the selectable frequencies, the bit rate, and the operating frequency. It also allows activating the automatic sleep feature and the automatic response to received bytes feature. 4.1.3 Transmit Upon detection of a start bit in HDI, the SIG40 starts to transmit modulated signal to the DC line according to the set-up channel frequency and bit rate. Note: After transmission, it takes duration of 2 bits before the device starts to listen to the DC-line. 4.1.4 Receive When not transmitting, the SIG40 listens to the DC line in order to: • Detect and decode a legal signaling pattern according to the setup channel and bit rate. • In Sleep mode, the device detects wakeup messages. • Detects Interference signals. Note: After transmission, it takes duration of 2 bits before the device starts to listen to the DC-line. 4.2 Control Registers 4.2.1 Device operating parameters and statuses The internal control registers shown in table 4.1 contain the device parameters and statuses: Register 0 7 6 5 4 3 2 1 0 Interference Sleep (“0”) ~F0/F1 Register 1 7 6 5 4 3 2 1 0 “1” “1” Bit rate Select frequency (table 4.2) Table 4.1 - Device Control Registers Address Register Name dir bits Description Default 0[0] F1/~F0 R/W 1 1 = F1, 0 = F0. F0 0[1] Remote loopback R/W 1 Transmits back the last received byte 0 0[3:2] For future use 00 |
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