CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *U
Page 4 of 50
3.3 The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows.
■ Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■ Filters (2 and 4 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
■ Modulators
■ Correlators
■ Peak Detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 3-2.
Figure 3-2. Analog System Block Diagram
3.3.1 The Analog Multiplexer System
The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing.
■ Chip-wide mux that enables analog input from up to 48 I/O pins.
■ Crosspoint connection between any I/O pin combinations.
AC B0 0
AC B0 1
Blo c k
A rra y
A r r ay In p u t
C o n fig u r a tio n
ACI1 [1 :0 ]
AS D 2 0
AC I0 [1 :0 ]
P0 [6 ]
P0 [4 ]
P0 [2 ]
P0 [0 ]
P2 [2 ]
P2 [0 ]
P2 [6 ]
P2 [4 ]
P0 [7 ]
P0 [5 ]
P0 [3 ]
P0 [1 ]
P2 [3 ]
P2 [1 ]
Re fe r e n c e
Ge n e r a t o r s
AG N D In
R e fIn
B a nd gap
Re fH i
Re fL o
AG N D
AS D 1 1
AS C 2 1
AS C 1 0
In te r face t o
Dig it a l S y s t e m
M 8 C In te r face (A d d r e s s B u s, D a t a B u s, E tc.)
An a lo g Re f e r e n c e
A ll IO
(E xc ep t P o r t 7)
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