TPS61185

SLVSAA1A – APRIL 2010 – REVISED MAY 2010

www.ti.com

PACKAGE

PACKAGE MARKING

TPS61185RGE

TPS61185

(1)

For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or visit the

device product folder on ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

–0.3

24

V

MODE

–0.3

7

V

SW

–0.3

40

V

EN, PWM, IFB1 to IFB8

–0.3

20

V

On all other pins

–0.3

3.6

V

See Thermal

Continuous power dissipation

Information Table

–40

150

°C

Temperature range

–65

150

°C

IFB1 to IFB8

5

Human Body Model (HBM)

kV

On all other pins

2

Machine Model (MM)

200

V

Charge Device Model (CDM)

1

kV

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

(3)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TPS61185

RGE

UNITS

24

33.7

16.9

7.4

°C/W

0.5

7.1

1.7

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

(6)

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

2

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): TPS61185