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OMAPL138AZCE3 Datasheet(PDF) 11 Page - Texas Instruments |
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OMAPL138AZCE3 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 268 page  OMAP-L138 Low-Power Applications Processor www.ti.com SPRS586A – JUNE 2009 – REVISED AUGUST 2009 Table 3-1. Characteristics of OMAP-L138 HARDWARE FEATURES OMAP-L138 DDR2, 16-bit bus width, up to 150 MHz DDR2/mDDR Controller Mobile DDR, 16-bit bus width, up to 133 MHz Asynchronous (8/16-bit bus width) RAM, Flash, EMIFA 16-bit SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported. 64 independent channels, 16 QDMA channels, EDMA3 2 channel controllers, 3 transfer controllers 4 64-Bit General Purpose (configurable as 2 separate 32-bit Timers timers, 1 configurable as Watch Dog) UART 3 (each with RTS and CTS flow control) SPI 2 (Each with one hardware chip select) I2C 2 (both Master/Slave) Peripherals Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) Not all peripherals pins are available at the Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16) same time (for more 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface) detail, see the Device Configurations section). 4 Single Edge, 4 Dual Edge Symmetric, or eHRPWM 2 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose Input/Output Port 9 banks of 16-bit LCD Controller 1 SATA Controller 1 (Support both SATA I and SATAII) Universal Parallel Port (uPP) 1 Video Port Interface (VPIF) 1 (video in and video out) PRU Subsystem (PRUSS) 2 Programmable PRU Cores Size (Bytes) 488KB RAM, 1088KB Boot ROM DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2) 1024KB ROM (L2) DSP Memories can be made accessible to ARM, EDMA3, and other peripherals. On-Chip Memory Organization ARM 16KB I-Cache 16KB D-Cache 8KB RAM (Vector Table) 64KB ROM ADDITIONAL SHARED MEMORY 128KB RAM C674x CPU ID + CPU Control Status Register (CSR.[31:16]) 0x1400 Rev ID C674x Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 Revision JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F 674x DSP 300 MHz CPU Frequency MHz ARM926 300 MHz 674x DSP 3.33 ns Cycle Time ns ARM926 3.33 ns Core (V) 1.2 V Voltage I/O (V) 1.8V or 3.3 V Submit Documentation Feedback Device Overview 11 |
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