74HC05_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 18 June 2009

3 of 13

NXP Semiconductors

74HC05

Hex inverter with open-drain outputs

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

7.

Limiting values

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 4.

Pin configuration SOT402-1 (TSSOP14)

Fig 5.

Pin configuration SOT762-1 (DHVQFN14)

74HC05

1A

1Y

6A

2A

6Y

2Y

5A

3A

5Y

3Y

4A

GND

4Y

001aak276

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aak277

74HC05

Transparent top view

3Y

4A

3A

5Y

2Y

5A

2A

6Y

1Y

6A

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

1A to 6A

1, 3, 5, 9, 11, 13

data input

1Y to 6Y

2, 4, 6, 8, 10, 12

data output

GND

7

ground (0 V)

14

supply voltage

Table 3.

Function table[1]

Input

Output

nA

nY

LZ

HL

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5

+7

V

input clamping current

[1] -20

mA

output clamping current

[1] -20

mA

output voltage

[1]

−0.5